Note: Complementary metal–oxide–semiconductor high voltage pulse generation circuits

2013 ◽  
Vol 84 (10) ◽  
pp. 106111 ◽  
Author(s):  
Jiwei Sun ◽  
Pingshan Wang
Keyword(s):  
Metal Oxide ◽  
High Voltage ◽  
Voltage Pulse ◽  
Complementary Metal Oxide Semiconductor ◽  
High Voltage Pulse ◽  
Metal Oxide Semiconductor ◽  
Pulse Generation ◽  
Oxide Semiconductor

scholarly journals A Regulated Temperature-Insensitive High-Voltage Charge Pump in Standard CMOS Process for Micromachined Gyroscopes

Sensors ◽  
2019 ◽  
Vol 19 (19) ◽  
pp. 4149
Author(s):  
Xiang Li ◽  
Rui Li ◽  
Chunge Ju ◽  
Bo Hou ◽  
Qi Wei ◽  
...  
Keyword(s):  
Metal Oxide ◽  
High Voltage ◽  
Output Voltage ◽  
Charge Pump ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Temperature Changes ◽  
Adjustable Range

Micromachined gyroscopes require high voltage (HV) for actuation and detection to improve its precision, but the deviation of the HV caused by temperature fluctuations will degrade the sensor’s performance. In this paper, a high-voltage temperature-insensitive charge pump is proposed. Without adopting BCD (bipolar-CMOS-DMOS) technology, the output voltage can be boosted over the breakdown voltage of n-well/substrate diode using triple-well NMOS (n-type metal-oxide-semiconductor) transistors. By controlling the pumping clock’s amplitude continuously, closed-loop regulation is realized to reduce the output voltage’s sensitivity to temperature changes. Besides, the output level is programmable linearly in a large range by changing the reference voltage. The whole circuit has been fabricated in a 0.18- μ m standard CMOS (complementary metal-oxide-semiconductor) process with a total area of 2.53 mm 2 . Measurements indicate that its output voltage has a linear adjustable range from around 13 V to 16.95 V, and temperature tests show that the maximum variations of the output voltage at − 40 ∼ 80 ∘ C are less than 1.1%.

Impacts of ESD Reliability by Different Layout Engineering in the 0.25-μm 60-V High-Voltage LDMOS Devices

2018 ◽  
Vol 3 (2) ◽  
Author(s):  
Shen-Li Chen ◽  
Chun-Ju Lin ◽  
Huang Yu-Ting
Keyword(s):  
Metal Oxide ◽  
High Voltage ◽  
Electrostatic Discharge ◽  
Complementary Metal Oxide Semiconductor ◽  
Narrow Channel ◽  
Metal Oxide Semiconductor ◽  
Channel Width ◽  
Oxide Semiconductor ◽  
Drain Side ◽  
Better Than

Abstract How to effectively enhance the reliability robustness in high-voltage (HV) BCD [(bipolar) complementary metal-oxide semiconductor (CMOS) diffusion metaloxide semiconductor (DMOS)] processes is an important issue. Influences of layouttype dependences on anti-electrostatic discharge (ESD) robustness in a 0.25-μm 60-V process will be studied in this chapter, which includes, in part (1), the traditional striped-type n-channel lateral-diffused MOSFET (nLDMOS), waffle-type nLDMOS, and nLDMOS embedded with a “p-n-p”-arranged silicon-controlled rectifier (SCR) devices in the drain side; and in part (2) a p-channel LDMOS (pLDMOS) with an embedded “p-n-p-n-p”-arranged-type SCR in the drain side (diffusion regions of the drain side is P+-N+-P+-N+-P+). Then, these LDMOS devices are used to evaluate the influence of layout architecture on trigger voltage (Vt1), holding voltage (Vh), and secondary breakdown current (It2). Eventually, the sketching of the layout pattern of a HV LDMOS is a very important issue in the anti-ESD consideration. Also, in part (1), the waffle-type nLDMOS DUT contributes poorly to It2 robustness due to the non-uniform turned-on phenomenon and a narrow channel width per unit finger. Therefore, the It2 robustness of a waffle-type nLDMOS device is decreased about 17% as compared to a traditional striped-type nLDMOS device (reference DUT-1). The ESD abilities of traditional stripedtype and waffle-type nLDMOS devices with an embedded SCR (“p-n-p”-manner arrangement in the drain side) are better than a traditional nLDMOS 224.4% in average. Noteworthy, the nLDMOS-SCR with the “p-n-p” -arranged-type in the drainend is a good structure for the anti-ESD reliability especially in HV usages. Furthermore, in part (2) this layout manner of P+ discrete-island distributions in the drain-side have some impacts on the anti-ESD and anti-latch-up (LU) immunities. All of their It2 values have reached above 6 A; however, the major repercussion is that the Vh value will be decreased about 66.7 ~ 73.7%.

Complementary metal oxide semiconductor compatible high-voltage transistors

1987 ◽  
Vol 65 (8) ◽  
pp. 1003-1008
Author(s):  
P. Kempf ◽  
R. Hadaway ◽  
J. Kolk
Keyword(s):  
Metal Oxide ◽  
High Voltage ◽  
Process Model ◽  
Low Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Electrical Measurements ◽  
Cmos Transistors

The purpose of this work was to study the implementation of high-voltage transistors using standard 3–5 μm complementary metal oxide semiconductor (CMOS) technology with a minimum of additional photolithographic or implant steps. A fabrication process was designed to accommodate a variety of high-voltage transistors with greater than 450 V breakdown voltage and low-voltage CMOS. Extensive use was made of a two-dimensional device model and a one-dimensional process model to determine suitable process parameters. The necessary conditions to produce a high-voltage double-diffused metal oxide semiconductor (DMOS) structure, as well as both n-well and p-well regions for CMOS transistors, and a thick gate oxide required to sustain the full blocking voltage were the main determinants of the process flow. Lateral DMOS (LDMOS), vertical DMOS (VDMOS), conductivity modulated FET (COMFET), and MOS triac (TRIMOS) devices were fabricated on the same chip as standard CMOS transistors using the developed fabrication sequence. This paper includes the results of the process modelling, device design, and electrical measurements.

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