Modulation of atomic-layer-deposited Al2O3film passivation of silicon surface by rapid thermal processing

2011 ◽  
Vol 99 (5) ◽  
pp. 052103 ◽  
Author(s):  
Dong Lei ◽  
Xuegong Yu ◽  
Lihui Song ◽  
Xin Gu ◽  
Genhu Li ◽  
...  
Keyword(s):  
Thermal Processing ◽  
Silicon Surface ◽  
Rapid Thermal Processing ◽  
Atomic Layer

Flash grafting of functional random copolymers for surface neutralization

2014 ◽  
Vol 2 (25) ◽  
pp. 4909-4917 ◽  
Author(s):  
F. Ferrarese Lupi ◽  
T. J. Giammaria ◽  
G. Seguini ◽  
M. Ceresoli ◽  
M. Perego ◽  
...  
Keyword(s):  
Thermal Processing ◽  
Silicon Surface ◽  
Rapid Thermal Processing ◽  
Random Copolymer ◽  
Random Copolymers ◽  
Grafting Reactions

Rapid Thermal Processing (RTP) technology was employed to perform flash grafting reactions of a hydroxyl terminated poly(styrene-r-methylmethacrylate) random copolymer to a silicon surface.

Rapid Thermal Processing-Based Heteroepitaxy: Material and Device Challenges

1995 ◽  
Vol 387 ◽  
Author(s):  
J. L. Hoyt ◽  
P. Kuo ◽  
K. Rim ◽  
J. J. Welser ◽  
R. M. Emerson ◽  
...  
Keyword(s):  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Atomic Layer ◽  
Layer Growth ◽  
Point Of View ◽  
Atomic Layer Epitaxy ◽  
Future Research ◽  
Layer By Layer ◽  
Limited Growth ◽  
Measurement And Control

AbstractMaterial and device challenges for Rapid Thermal Processing (RTP) of heterostructures are discussed, focusing on RTP-based epitaxy in the Si/Si1−xGex system. While RTP-based heteroepitaxy offers enhanced processing flexibility, it also poses significant challenges for temperature measurement and control. Several examples of Si/Si1−xGex device structures are discussed from the point of view of the sensitivity of device parameters to variations in layer thickness and composition. The measured growth kinetics for Si and Si1−xGex are then used to estimate growth temperature tolerances for these structures. Demanding applications are expected to require temperature control and uniformity to within 0.5°C.Future research challenges include the fabrication of structures with monolayer thickness control using self-limited growth techniques. Atomic layer epitaxy (ALE) is a well-known example of such a growth technique. In ALE, the wafer is cyclically exposed to different reactants, to achieve layer-by-layer growth. An RTP-based atomic layer epitaxy process, and its application to the growth of CdTe films, is briefly discussed. The extension to Column IV alloys follows readily. The RTP-based process enables self-limited growth for precursor combinations for which isothermal ALE is not feasible.

On the Contacts Formed in Ni-Al-Si System Due to Localized Melting by Means of Rapid Thermal Processing

1988 ◽  
Vol 100 ◽  
Author(s):  
A. Katz ◽  
Y. Komem
Keyword(s):  
Schottky Barrier ◽  
Barrier Height ◽  
Thermal Processing ◽  
Silicon Surface ◽  
Schottky Barrier Height ◽  
Rapid Thermal Processing ◽  
Solidification Process ◽  
Eutectic Liquid ◽  
Eutectic Melting ◽  
Rapid Melting

ABSTRACTLocalized rapid melting of an intermediate Al film in the Ni(30nm)/Al(10nm)/<100>n-Si system was successfully carried out by means of rapid thermal processing at temperatures higher than 580°C. This rapid melting resulted in the formation of a unique metal-silicon contact composed of three separated layers and has the following structure: Ni(Al0.5,Si0.5)/Al3 Ni/NiSi / <100>n-Si. It was found on the basis of quenching treatments after subsequent rapid thermal processings that an eutectic melting initiated at the Al-Si interface at 580°C, propagated towards the Ni layer and then formed a localized melt zone confined mainly to the region of the intermediate Al layer. The formation of the nickel silicides took place at the silicon surface after Ni diffusion through the melt zone, while the Al compounds were formed during a solidification process of the eutectic liquid. The eutectic melting at 580°C led to the decrease of the sheet resistance of the formed films from 3.2 to 2.6 / and to the increase of the Schottky barrier height of the contact from 0.6 to 0.76 eV.

In-Situ Processing of Silicon Dielectrics by Rapid Thermal Processing: Cleaning, Growth, and Annealing

1987 ◽  
Vol 92 ◽  
Author(s):  
J. Nulman
Keyword(s):  
Thermal Processing ◽  
Silicon Surface ◽  
Rapid Thermal Processing ◽  
Oxide Growth ◽  
Surface Chemical ◽  
Native Oxides ◽  
Wafer Cleaning ◽  
In Situ Processing ◽  
Kinetics Of

ABSTRACTThe in-situ processing of silicon dielectrics by rapid thermal processing (RTP) is described. RTP includes here three basic sequentially performed processes: wafer cleaning, oxidation and annealing. The insitu cleaning allows for reduction of chemical and native oxides and silicon surface chemical polish, resulting in interface density of states as low as 5×l09 cm-2eV-1. Kinetics of oxide growth indicates an activation energy of 1.4 eV for the initial linear oxidation rate.

Gas Flow Engineering in Rapid Thermal Processing

1994 ◽  
Vol 342 ◽  
Author(s):  
Z. Nényei ◽  
H. Sommer ◽  
J. Gelpey ◽  
A. Bauer
Keyword(s):  
Low Temperature ◽  
Thermal Processing ◽  
Gas Dynamics ◽  
Silicon Surface ◽  
Gas Flow ◽  
Rapid Thermal Processing ◽  
Inert Gas ◽  
Guard Ring ◽  
Interface Damage ◽  
Bottom Heater

ABSTRACTGas flow engineering involves gas dynamics optimization for effective ambient change before heating and for homogeneous convective cooling of the wafers during the heating steps. Multiple gas buffle system, dynamical gas handling, low pressure operation, low temperature edge guard ring and independent top and bottom heater bank control are the proper tools for this optimization. Silicon surface or interface damage during inert gas anneal can be avoided by addition of a small amount of oxygen.

Rapid thermal processing of hafnium dioxide thin films by remote plasma atomic layer deposition as high-k dielectrics

2018 ◽  
Vol 660 ◽  
pp. 797-801 ◽  
Author(s):  
Xiao-Ying Zhang ◽  
Chia-Hsun Hsu ◽  
Yun-Shao Cho ◽  
Sam Zhang ◽  
Shui-Yang Lien ◽  
...  
Keyword(s):  
Thin Films ◽  
Atomic Layer Deposition ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Atomic Layer ◽  
Hafnium Dioxide ◽  
Remote Plasma ◽  
Layer Deposition ◽  
High K

Point Defect Reaction in Silicon Wafers by Rapid Thermal Processing at More Than 1300°C Using an Oxidation Ambient

2019 ◽  
Vol 8 (1) ◽  
pp. P35-P40 ◽  
Author(s):  
Haruo Sudo ◽  
Kozo Nakamura ◽  
Susumu Maeda ◽  
Hideyuki Okamura ◽  
Koji Izunome ◽  
...  
Keyword(s):  
Point Defect ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Silicon Wafers ◽  
Defect Reaction
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