scholarly journals A versatile low-temperature setup for the electrical characterization of single-molecule junctions

2011 ◽  
Vol 82 (5) ◽  
pp. 053907 ◽  
Author(s):  
Christian A. Martin ◽  
Roel H. M. Smit ◽  
Ruud van Egmond ◽  
Herre S. J. van der Zant ◽  
Jan M. van Ruitenbeek
Keyword(s):  
Low Temperature ◽  
Single Molecule ◽  
Electrical Characterization ◽  
Single Molecule Junctions

Electrical Characterization of Low Temperature GaAs Layers, and Observation of the Extremely Large Carrier Concentrations in Undoped Material

1991 ◽  
Vol 241 ◽  
Author(s):  
Bijan Tadayon ◽  
Mohammad Fatemi ◽  
Saied Tadayon ◽  
F. Moore ◽  
Harry Dietrich
Keyword(s):  
Molecular Beam Epitaxy ◽  
Low Temperature ◽  
Substrate Temperature ◽  
Molecular Beam ◽  
Electrical Characterization ◽  
Physical Characteristics ◽  
Hall Measurements ◽  
Undoped Material ◽  
Low Temperature Gaas

ABSTRACTWe present here the results of a study on the effect of substrate temperature, Ts, on the electrical and physical characteristics of low temperature (LT) molecular beam epitaxy GaAs layers. Hall measurements have been performed on the asgrown samples and on samples annealed at 610 °C and 850 °C. Si implantation into these layers has also been investigated.

Electrical Characterization of Low Temperature PECVD Oxides for TSV Applications

2018 ◽  
Vol 2018 (1) ◽  
pp. 000728-000733
Author(s):  
Piotr Mackowiak ◽  
Rachid Abdallah ◽  
Martin Wilke ◽  
Jash Patel ◽  
Huma Ashraf ◽  
...  
Keyword(s):  
Low Temperature ◽  
Electrical Characterization ◽  
Chemical Vapor ◽  
Silicon Substrates ◽  
Low Temperature Plasma ◽  
Temperature Plasma ◽  
Charge Densities ◽  
Doped Silicon

Abstract In the present work we investigate the quality of low temperature Plasma Enhanced Chemical Vapor Deposition (PECVD) and plasma treated Tetraethyl orthosilicate (TEOS)-based TSV-liner films. Different designs of Trough Silicon Via (TSV) Test structures with 10μm and 20μm width and a depth of 100μm have been fabricated. Two differently doped silicon substrates have been used – highly p-doped and moderately doped. The results for break-through, resistivity and capacitance for the 20μm structures show a better performance compared to the 10μm structures. This is mainly due to increased liner thickness in the reduced aspect ratio case. Lower interface traps and oxide charge densities have been observed in the C-V measurements results for the 10μm structures.

Electrical characterization of low‐temperature Al0.3Ga0.7As using n‐i‐n structures

1996 ◽  
Vol 68 (5) ◽  
pp. 699-701 ◽  
Author(s):  
A. K. Verma ◽  
J. Tu ◽  
J. S. Smith ◽  
H. Fujioka ◽  
E. R. Weber
Keyword(s):  
Low Temperature ◽  
Electrical Characterization

Omvpe Growth and Characterization of GaAs on Si for Device Applications

1988 ◽  
Vol 116 ◽  
Author(s):  
S. K. Shastry ◽  
S. Zemon ◽  
C. Armiento ◽  
M. B. Stern ◽  
M. Levinson ◽  
...  
Keyword(s):  
Low Temperature ◽  
Electrical Characterization ◽  
Spectral Width ◽  
Growth Technique ◽  
Temperature Growth ◽  
Vanadium Doping ◽  
Device Applications ◽  
First Time ◽  
Made In

AbstractSignificant progress has been made in the OMVPE growth of GaAs directly on Si by the previously reported low-temperature growth technique. These films have been characterized by low-temperature PL, SIMS, TEM, and DLTS. The epitaxial layers, whose quality has been determined by PL measurements (4.2 K PL spectral width of heavy-hole exciton ≈ 3 meV), were implanted with 29Si+ for fabrication of MESFET channels. Background concentrations of ≈ 1014 cm−3 have been achieved for the first time after rapid thermal annealing without the need to use oxygen implantation or vanadium doping. SIMS measurements do not show Si pileup on the surface or much Si diffusion at the GaAs-Si interface, a significant improvement over earlier results. DLTS measurements and electrical characterization of the GaAs-Si heterojunction diode indicate the presence of only two trap levels (< 1014 cm−3 in concentration) in the GaAs ≥ 2.5 μm away from the interface.

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