Effects of back interface trap states on the fully depleted strained-silicon-on-insulator capacitorless single transistor dynamic random access memory cells

2010 ◽  
Vol 97 (15) ◽  
pp. 152105 ◽  
Author(s):  
Min-Soo Kim ◽  
Won-Ju Cho
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Silicon On Insulator ◽  
Strained Silicon ◽  
Interface Trap ◽  
Memory Cells ◽  
Trap States ◽  
Access Memory ◽  
Fully Depleted

Analysis of Grain Boundary Dependent Memory Characteristics in Poly-Si One-Transistor Dynamic Random-Access Memory

2021 ◽  
Vol 21 (8) ◽  
pp. 4216-4222
Author(s):  
Songyi Yoo ◽  
In-Man Kang ◽  
Sung-Jae Cho ◽  
Wookyung Sun ◽  
Hyungsoon Shin
Keyword(s):  
Strong Electric Field ◽  
Memory Performance ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Thin Body ◽  
Memory Cells ◽  
Access Memory ◽  
Memory Characteristics

A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory’s data state. In this paper, we report on a statistical analysis of the memory characteristics of poly-Si 1T-DRAM cells according to the number and location of GBs using TCAD simulation. As the number of GBs increases, the sensing margin and retention time of memory cells deteriorate due to increasing trapped electron charge. Also, “0” state current increases and memory performance degrades in cells where all GBs are adjacent to the source or drain junction side in a strong electric field. These results mean that in poly-Si 1T-DRAM design, the number and location of GBs in a channel should be considered for optimal memory performance.

Analysis of the Use of Molecular Resonant Tunneling Diodes for Local Refresh of Dynamic Random Access Memory Cells

2001 ◽  
Vol 679 ◽  
Author(s):  
Jonas Berg ◽  
Stefan Bengtsson ◽  
Per Lundgren
Keyword(s):  
Electrical Properties ◽  
Resonant Tunneling ◽  
Random Access ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Storage Capacitor ◽  
Resonant Tunneling Diodes ◽  
Memory Cells ◽  
Access Memory ◽  
Tunneling Diodes

ABSTRACTSimulations have been made to analyze the use of molecular resonant tunneling diodes for local refresh of DRAM (Dynamic Random Access Memory) cells. Local refresh can be provided by a latch consisting of a pair of resonant tunneling diodes connected to the storage capacitor of the cell. Such a solution would significantly reduce the standby power consumption of the DRAM cell. We have compared the requirements on the resonant tunneling diodes for proper refresh operation with the electrical properties of published molecules with resonant IV-curves. The simulations show that no molecules with resonant electrical properties published so far in the literature have properties making them useful for this particular application. This is true also for low temperature operation. The issues of maximum tolerable series resistance and of maximum tolerable fluctuations in the number of attached molecules have also been addressed. Our results show that the focus for development of molecules with resonant electrical properties should be to find molecules with resonance for lower applied voltages and lower current levels than the molecules published so far. If the synthesis of new molecules with attractive properties is successful the merging of silicon technology and molecular electronics, for instance for new generations of DRAM cells, is a realistic future path of microelectronics.

scholarly journals Optimization Considerations for Short Channel Poly-Si 1T-DRAM

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 1051 ◽  
Author(s):  
Songyi Yoo ◽  
Woo-Kyung Sun ◽  
Hyungsoon Shin
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
The Body ◽  
Dynamic Random Access Memory ◽  
Thin Body ◽  
Memory Cells ◽  
Transient Performance ◽  
Drain Voltage ◽  
Access Memory ◽  
Short Channel

Capacitorless one-transistor dynamic random-access memory cells that use a polysilicon body (poly-Si 1T-DRAM) have been studied to overcome the scaling issues of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Generally, when the gate length of a silicon-on-insulator (SOI) structure metal-oxide-silicon field-effect transistor (MOSFET) is reduced, its body thickness is reduced in order to suppress the short-channel effects (SCEs). TCAD device simulations were used to investigate the transient performance differences between thin and thick-body poly-Si DRAMs to determine whether reduced body thickness is also appropriate for those devices. Analysis of the simulation results revealed that operating bias conditions are as important as body thickness in 1T-DRAM operation. Since a thick-body device has more trapped hole charge in its grain boundary (GB) than a thin-body device in both the “0” and “1” states, the transient performance of a thick-body device is better than a thin-body device regardless of the Write”1” drain voltage. We also determined that the SCEs in the memory cells can be improved by lowering the Write”1” drain voltage. We conclude that an optimization method for the body thickness and voltage conditions that considers both the cell’s SCEs and its transient performance is necessary for its development and application.

scholarly journals Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM

Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 228
Author(s):  
Hyeonjeong Kim ◽  
Songyi Yoo ◽  
In-Man Kang ◽  
Seongjae Cho ◽  
Wookyung Sun ◽  
...  
Keyword(s):  
Three Dimensional ◽  
Random Access ◽  
Random Access Memory ◽  
Cost Effective ◽  
Dynamic Random Access Memory ◽  
Silicon On Insulator ◽  
Floating Body ◽  
Thin Body ◽  
Access Memory ◽  
The Cost

Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Poly-Si 1T-DRAM enables the cost-effective implementation of a silicon-on-insulator (SOI) structure and a three-dimensional (3D) stacked architecture for increasing integration density. However, studies on the transient characteristics of poly-Si 1T-DRAM are still lacking. In this paper, with TCAD simulation, we examine the differences between the memory mechanisms in poly-Si and silicon body 1T-DRAM. A silicon 1T-DRAM cell’s data state is determined by the number of holes stored in a floating body (FB), while a poly-Si 1T-DRAM cell’s state depends on the number of electrons trapped in its grain boundary (GB). This means that a poly-Si 1T-DRAM can perform memory operations by using GB as a storage region in thin body devices with a small FB area.

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