Scaling equivalent oxide thickness with flat band voltage (VFB) modulation using in situ Ti and Hf interposed in a metal/high-k gate stack

2010 ◽  
Vol 108 (6) ◽  
pp. 064107 ◽  
Author(s):  
Changhwan Choi ◽  
Jack C. Lee
Keyword(s):  
Oxide Thickness ◽  
Flat Band ◽  
Flat Band Voltage ◽  
Equivalent Oxide Thickness ◽  
Gate Stack ◽  
High K

In-Situ Deposition of High-k Gate Stack on InGaAs and GaAs for Metal-Oxide-Semiconductor Devices with Low Equivalent Oxide Thickness

2019 ◽  
Vol 11 (4) ◽  
pp. 431-439 ◽  
Author(s):  
Rama Kambhampati ◽  
Sergei Koveshnikov ◽  
Vadim Tokranov ◽  
M. Yakimov ◽  
R Moore ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Semiconductor Devices ◽  
Oxide Thickness ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Equivalent Oxide Thickness ◽  
Gate Stack ◽  
In Situ Deposition ◽  
High K

Strategies for CMOS Low Equivalent Oxide Thickness Achievement with High-κ Oxides Grown on Si(001) by MBE

2008 ◽  
Vol 1073 ◽  
Author(s):  
Loic Becerra ◽  
Clément Merckling ◽  
Nicolas Baboux ◽  
Mario El-Kazzi ◽  
Guillaume Saint-Girons ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Molecular Beam ◽  
Oxide Thickness ◽  
Flat Band ◽  
Equivalent Oxide Thickness ◽  
Electrical Measurements ◽  
X Ray ◽  
High K ◽  
Density Of Interface States ◽  
Post Deposition

ABSTRACTAmorphous LaAlO3 high-k oxide was grown in a molecular beam epitaxy reactor on p-Si(001) using a thin γ-Al2O3 epitaxied buffer layer. Interfaces were free of SiO2 or silicates and remained abrupt despite the high temperature used for annealing, as X-ray photoelectron spectroscopy showed. Electrical measurements performed on as-deposited samples revealed a dielectric constant value close to that of the bulk, small equivalent oxide thickness and low density of interface states. But some negative charges were present, leading to a flat band voltage shift. Post deposition annealing with forming gas can correct this effect.

CHALLENGES AND PROGRESS IN III-V MOSFETs FOR CMOS CIRCUITS

2008 ◽  
Vol 18 (04) ◽  
pp. 761-772 ◽  
Author(s):  
SERGE OKTYABRSKY ◽  
MICHAEL YAKIMOV ◽  
VADIM TOKRANOV ◽  
RAMA KAMBHAMPATI ◽  
HASSARAM BAKHRU ◽  
...  
Keyword(s):  
Oxide Thickness ◽  
Passivation Layer ◽  
Equivalent Oxide Thickness ◽  
Channel Mobility ◽  
High K ◽  
Amorphous Si ◽  
Sputter Deposited ◽  
Interface Passivation ◽  
Effective Channel

An overview of III-V MOSFET technological challenges in comparison to well-established heterostructure-based FET technologies is presented with an emphasis on required properties and possible solutions. Possible approaches to achieve thermodynamically stable high- k gate stack with low interface trap density are reviewed, followed with our results on amorphous Si interface passivation layer (IPL) in-situ deposited on top of GaAs or strained InGaAs MOSFET channels grown by molecular beam epitaxy. Main issues of Si IPL, namely increased equivalent oxide thickness due to IPL oxidation and Si diffusion into the semiconductor channel, are addressed using an in-situ deposited HfO 2 with ultrathin (down to 0.25 nm) Si IPL and controlling its bonding state at the interface. Enhancement mode inversion-type MOSFET with HfO 2 high- k oxide is demonstrated. The device employs amorphous Si interface passivation layer, sputter-deposited high- k oxide and metal TaN gate and modulation p-doped GaAs / AlGaAs heterostructure with inversion n -channel formed at the interface with the oxide. The MOSFET with equivalent oxide thickness of 3.7 nm and long 100 μm channel have maximum DC transonductance of 0.9 mS/mm, Ion/Ioff = 2×104 (at low Ioff of 30 nA) and effective channel mobility exceeding 1000 cm2/V-s at sheet electron density <2×1012 cm-2.

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