Image processing with cellular nonlinear networks implemented on field-programmable gate arrays for real-time applications in nuclear fusion

2010 ◽  
Vol 81 (8) ◽  
pp. 083505 ◽  
Author(s):  
S. Palazzo ◽  
A. Murari ◽  
G. Vagliasindi ◽  
P. Arena ◽  
D. Mazon ◽  
...  
Keyword(s):  
Image Processing ◽  
Real Time ◽  
Nuclear Fusion ◽  
Field Programmable Gate Arrays ◽  
Nonlinear Networks ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Real Time Applications

MISS RATIO IMPROVEMENT FOR REAL-TIME APPLICATIONS USING FRAGMENTATION-AWARE PLACEMENT

2007 ◽  
Vol 16 (06) ◽  
pp. 997-1010
Author(s):  
AHMED A. ELFARAG ◽  
HATEM M. El-BOGHDADI ◽  
SAMIR I. SHAHEEN
Keyword(s):  
Real Time ◽  
Field Programmable Gate Arrays ◽  
Gate Arrays ◽  
Placement Method ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Bottom Left ◽  
Real Time Applications ◽  
Online Placement ◽  
Best Fit

Partially reconfigurable field-programmable gate arrays (FPGAs) allow parts of the chip to be configured at runtime where each part could hold an independent task. Online placement of these tasks result in area fragmentation leading to poor utilization of chip resources. In this paper, we propose a new metric for measuring area fragmentation. The new fragmentation metric gives an indication to the continuity of the occupied (or free) space and not the amount of occupied space. We show how this metric can be extended for multidimensional structures. We also show how this metric can be computed efficiently at runtime. Next, we use this measure during online placement of tasks on FPGAs, such that the chip fragmentation is reduced. Our results show improvement of chip utilization when using this fragmentation aware placement method over other placement methods with well-known bottom left, first fit, and best-fit placement strategies. In real-time environment, we achieve an improvement in miss ratio when using the fragmentation-aware placement over the bottom left placement strategy.

Building Information Modeling using Hardware Genetic Algorithms with Field-Programmable Gate Arrays

2014 ◽  
Vol 5 (4) ◽  
pp. 24-49 ◽  
Author(s):  
Khoa N. Le ◽  
Ivan W. H. Fung ◽  
Vivian W. Y. Tam ◽  
Leslie Yip ◽  
Eric W. M. Lee
Keyword(s):  
Genetic Algorithms ◽  
Real Time ◽  
Building Information Modeling ◽  
Field Programmable Gate Arrays ◽  
Information Modeling ◽  
Gate Arrays ◽  
Building Information ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Real Time Applications

Genetic algorithms (GAs) have found many applications in various fields such as physics, signal processing, artificial intelligence and recently construction engineering management. For a long time, GAs are usually criticized to be time-consuming, making it unpractical for real-time applications. This paper presents a new technique which can be used: (1) to automate construction activities, and (2) to improve building information modeling which has become an attractive research topic around the world. Different from the generic GA techniques employed in the literature, this paper proposes a new GA using hardware with field-programmable gate arrays. The proposed technique is shown to improve speed and lessen computational power. Hardware implementation of GA using static random access memory-based field-programmable gate arrays with synthesizable very hardware description language coding is introduced. Detailed analyses on the field-programmable gate arrays are given which show that it is suitable for real-time applications. As a result, GA is modified so that it can be implemented in series and parallel which can greatly improve computational hardware performance. Configuration of parallelization is available with a peripheral component interconnect interface, which further helps to form a fast optimization tool for real-time applications. The ultimate goal of this paper is thus to design an effective GA technique which can be employed to support building information modeling and to effectively automate critical processes in construction projects.

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