Heteroepitaxy of GexSi1−xon porous Si substrates

1990 ◽  
Vol 67 (2) ◽  
pp. 792-795 ◽  
Author(s):  
Y. H. Xie ◽  
J. C. Bean
Keyword(s):  
2021 ◽  
Vol 16 (1) ◽  
Author(s):  
Yijie Li ◽  
Nguyen Van Toan ◽  
Zhuqing Wang ◽  
Khairul Fadzli Bin Samat ◽  
Takahito Ono

AbstractPorous silicon (Si) is a low thermal conductivity material, which has high potential for thermoelectric devices. However, low output performance of porous Si hinders the development of thermoelectric performance due to low electrical conductivity. The large contact resistance from nonlinear contact between porous Si and metal is one reason for the reduction of electrical conductivity. In this paper, p- and n-type porous Si were formed on Si substrate by metal-assisted chemical etching. To decrease contact resistance, p- and n-type spin on dopants are employed to dope an impurity element into p- and n-type porous Si surface, respectively. Compared to the Si substrate with undoped porous samples, ohmic contact can be obtained, and the electrical conductivity of doped p- and n-type porous Si can be improved to 1160 and 1390 S/m, respectively. Compared with the Si substrate, the special contact resistances for the doped p- and n-type porous Si layer decreases to 1.35 and 1.16 mΩ/cm2, respectively, by increasing the carrier concentration. However, the increase of the carrier concentration induces the decline of the Seebeck coefficient for p- and n-type Si substrates with doped porous Si samples to 491 and 480 μV/K, respectively. Power factor is related to the Seebeck coefficient and electrical conductivity of thermoelectric material, which is one vital factor that evaluates its output performance. Therefore, even though the Seebeck coefficient values of Si substrates with doped porous Si samples decrease, the doped porous Si layer can improve the power factor compared to undoped samples due to the enhancement of electrical conductivity, which facilitates its development for thermoelectric application.


Author(s):  
Pablo Cano ◽  
Manuel Hinojosa ◽  
Luis Cifuentes ◽  
Huy Nguyen ◽  
Aled Morgan ◽  
...  

2001 ◽  
Author(s):  
Ziqiang Zhu ◽  
Yanling Shi ◽  
Yongfu Long ◽  
Peisheng Xin ◽  
Zongsheng Lai

2018 ◽  
Vol 7 (9) ◽  
pp. P480-P486 ◽  
Author(s):  
S. A. Kukushkin ◽  
Sh. Sh. Sharofidinov ◽  
A. V. Osipov ◽  
A. V. Redkov ◽  
V. V. Kidalov ◽  
...  

2002 ◽  
Vol 23 (3) ◽  
pp. 160-162 ◽  
Author(s):  
Han-Su Kim ◽  
K.A. Jenkins ◽  
Ya-Hong Xie
Keyword(s):  

2013 ◽  
Vol 27 (08) ◽  
pp. 1350051 ◽  
Author(s):  
ALIREZA BIARAM ◽  
HOSEIN ESHGHI

We have fabricated SnO 2/p- Si and SnO 2/p- PoSi heterojunction diodes by spray pyrolysis method. To prepare porous Si substrates, the etching time was varied from 10 to 20 and 30 mins. In these samples, the SEM micrographs showed a distributed pore areas surrounded by columnar walls with various height. The data analysis of the rectified I–V characteristic, using thermionic emission Schottky diode theory, showed that although the barrier height is about 0.5–0.6 eV in all samples other two important diode parameters, i.e. the ideality factor n and the series resistance rs, are strongly etching time-dependant and are increased with increasing the etching time.


1992 ◽  
Vol 281 ◽  
Author(s):  
A. J. Steckl ◽  
J. Xu ◽  
H. C. Mogul ◽  
S. Mogren

ABSTRACTThe effect of Si doping on the formation of stain-etched porous Si and its photoluminescent properties was studied. Porous Si is obtained by purely chemical etching of crystalline Si in a solution of HF:HNO3:H2O in the ratio of 1:3:5. We have observed that an incubation time (ti) exists between the insertion of Si into the solution and the onset of porous Si production. This incubation time was found to be a strong function of hole concentration in both n- and p-Si. In p-Si, the ti decreased rapidly with increasing conductivity, whereas for n-Si the opposite (but not as pronounced) trend was found to be the case. For example in (B-doped) p-Si, ti, is only ∼0.5 min for 250 (Ω-cm)−1 but increases to ∼ 5 min for 0.2 (Ω-cm)−1. In (P-doped) n-Si substrates ti was ∼ 8 min for 0.2 (Ω-cm)−1 increasing to ∼ 10 min for 7 (Ω-cm)−1. Photoluminescence (PL) measurements of the porous Si obtained on substrates of various conductivity (p and n) show similar spectra, namely a peak at around 1.94 eV with a full width at half-maximum (FWHM) of about 0.5 eV. Based on the ti difference, we have fabricated localized photoemitting porous Si patterns by Ga+ focused ion beam (FIB) implantation doping and B+ broad beam (BB) implantation doping of n-type Si. Using 30 kV FIB Ga+ implantation, sub-micron photoemitting patterns have been obtained for the first time.


2000 ◽  
Vol 15 (12) ◽  
pp. 2602-2605 ◽  
Author(s):  
T. W. Kang ◽  
S. H. Park ◽  
T. W. Kim

A new approach was used for combining GaN and porous Si with the goal of producing high-quality GaN epitaxial layers for optoelectronic integrated circuit devices based on Si substrates. Reflection high-energy electron diffraction (RHEED), x-ray diffraction (XRD), photoluminescence (PL), and Van der Pauw–Hall effect measurements were performed to investigate the structural, optical, and electrical properties of the GaN epitaxial films grown on porous Si(100) by plasma-assisted molecular-beam epitaxy with a two-step method. The RHEED patterns were streaky with clear Kikuchi lines, which was direct evidence for layer-by-layer two-dimensional growth of GaN epitaxial layers on porous Si layers. The XRD curves showed that the grown layers were GaN(0001) epitaxial films. The results of the XRD and the PL measurements showed that the crystallinities of the GaN epilayers grown on porous Si by using a two-step growth were remarkably improved because the porous Si layer reduced the strains in the GaN epilayers by sharing them with the Si substrates. Hall-effect measurements showed that the mobility of the GaN active layer was higher than that of the GaN initial layer. These results indicate that high-quality GaN epitaxial films grown on porous Si(100) by using two-step growth hold promise for potential applications in new kinds of optoelectronic monolithic and ultralarge integrated circuits.


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