Josephson 4 K‐bit cache memory design for a prototype signal processor. III. Decoding, sensing, and timing

1985 ◽  
Vol 58 (6) ◽  
pp. 2389-2399 ◽  
Author(s):  
W. H. Henkels ◽  
L. M. Geppert ◽  
J. Kadlec ◽  
P. W. Epperlein ◽  
H. Beha ◽  
...  
Keyword(s):  
Cache Memory ◽  
Memory Design ◽  
Signal Processor

Josephson 4 K‐bit cache memory design for a prototype signal processor. II. Cell array and drivers

1985 ◽  
Vol 58 (6) ◽  
pp. 2379-2388 ◽  
Author(s):  
W. H. Henkels ◽  
L. M. Geppert ◽  
J. Kadlec ◽  
P. W. Epperlein ◽  
H. Beha ◽  
...  
Keyword(s):  
Cache Memory ◽  
Cell Array ◽  
Memory Design ◽  
Signal Processor

Josephson 4 K‐bit cache memory design for a prototype signal processor. I. General overview

1985 ◽  
Vol 58 (6) ◽  
pp. 2371-2378 ◽  
Author(s):  
W. H. Henkels ◽  
L. M. Geppert ◽  
J. Kadlec ◽  
P. W. Epperlein ◽  
H. Beha ◽  
...  
Keyword(s):  
Cache Memory ◽  
Memory Design ◽  
General Overview ◽  
Signal Processor

Efficient fault tolerant cache memory design

1995 ◽  
Vol 41 (2) ◽  
pp. 153-169 ◽  
Author(s):  
H.T. Verges ◽  
D. Nikolos
Keyword(s):  
Fault Tolerant ◽  
Cache Memory ◽  
Memory Design
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