Scalable Iterative Solvers Applied to 3D Parallel Simulation of Advanced Semiconductor Devices

2009 ◽  
Author(s):  
A. J. García-Loureiro ◽  
M. Aldegunde ◽  
N. Seoane ◽  
George Maroulis ◽  
Theodore E. Simos
Keyword(s):  
Semiconductor Devices ◽  
Parallel Simulation ◽  
Iterative Solvers

Parallel Simulation of Semiconductor Devices

1994 ◽  
pp. 683-690 ◽  
Author(s):  
I.R. Barker ◽  
A. Asenov ◽  
A.R. Brown ◽  
J. Cluckie ◽  
S. Babiker ◽  
...  
Keyword(s):  
Semiconductor Devices ◽  
Parallel Simulation

Formation of defects in implanted hipox-structures

1992 ◽  
Vol 50 (2) ◽  
pp. 1406-1407
Author(s):  
Peter Pegler ◽  
N. David Theodore ◽  
Ming Pan
Keyword(s):  
High Pressure ◽  
Cross Section ◽  
Semiconductor Devices ◽  
Silicon Substrates ◽  
Processing Conditions ◽  
Pressure Oxidation ◽  
Deep Trench ◽  
Local Oxidation ◽  
Trench Isolation ◽  
And Behavior

High-pressure oxidation of silicon (HIPOX) is one of various techniques used for electrical-isolation of semiconductor-devices on silicon substrates. Other techniques have included local-oxidation of silicon (LOCOS), poly-buffered LOCOS, deep-trench isolation and separation of silicon by implanted oxygen (SIMOX). Reliable use of HIPOX for device-isolation requires an understanding of the behavior of the materials and structures being used and their interactions under different processing conditions. The effect of HIPOX-related stresses in the structures is of interest because structuraldefects, if formed, could electrically degrade devices.This investigation was performed to study the origin and behavior of defects in recessed HIPOX (RHIPOX) structures. The structures were exposed to a boron implant. Samples consisted of (i) RHlPOX'ed strip exposed to a boron implant, (ii) recessed strip prior to HIPOX, but exposed to a boron implant, (iii) test-pad prior to HIPOX, (iv) HIPOX'ed region away from R-HIPOX edge. Cross-section TEM specimens were prepared in the <110> substrate-geometry.

Comparison of ultra high resolution immersion lens CFESEM and TEM for imaging of semiconductor devices

1990 ◽  
Vol 48 (4) ◽  
pp. 622-623
Author(s):  
Terrence Reilly ◽  
Al Pelillo ◽  
Barbara Miner
Keyword(s):  
High Resolution ◽  
Sample Preparation ◽  
Cross Sections ◽  
Semiconductor Devices ◽  
Ion Milling ◽  
Observation Area ◽  
Transmission Electron ◽  
Milling Machines ◽  
Resolution Imaging ◽  
Electron Microscopes

The use of transmission electron microscopes (TEM) has proven to be very valuable in the observation of semiconductor devices. The need for high resolution imaging becomes more important as the devices become smaller and more complex. However, the sample preparation for TEM observation of semiconductor devices have generally proven to be complex and time consuming. The use of ion milling machines usually require a certain degree of expertise and allow a very limited viewing area. Recently, the use of an ultra high resolution "immersion lens" cold cathode field emission scanning electron microscope (CFESEM) has proven to be very useful in the observation of semiconductor devices. Particularly at low accelerating voltages where compositional contrast is increased. The Hitachi S-900 has provided comparable resolution to a 300kV TEM on semiconductor cross sections. Using the CFESEM to supplement work currently being done with high voltage TEMs provides many advantages: sample preparation time is greatly reduced and the observation area has also been increased to 7mm. The larger viewing area provides the operator a much greater area to search for a particular feature of interest. More samples can be imaged on the CFESEM, leaving the TEM for analyses requiring diffraction work and/or detecting the nature of the crystallinity.

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