Copper ion drift in integrated circuits: Effect of boundary conditions on reliability and breakdown of low-k dielectrics

2008 ◽  
Vol 103 (1) ◽  
pp. 014907 ◽  
Author(s):  
Ravi S. Achanta ◽  
William N. Gill ◽  
Joel L. Plawsky
Keyword(s):  
Integrated Circuits ◽  
Boundary Conditions ◽  
Copper Ion ◽  
Ion Drift ◽  
Low K

Study of Porous Silica Based Films as Low-k Dielectric Material and their Interface with Copper Metallization

2002 ◽  
Vol 716 ◽  
Author(s):  
Ilanit Fisher ◽  
Wayne D. Kaplan ◽  
Moshe Eizenberg ◽  
Michael Nault ◽  
Timothy Weidman
Keyword(s):  
Integrated Circuits ◽  
Dielectric Material ◽  
Hydrogen Plasma ◽  
Porous Silica ◽  
Film Deposition ◽  
Copper Metallization ◽  
High Porosity ◽  
Tem Analysis ◽  
Chip Technology ◽  
Low K

AbstractThe success of future gigascale integrated circuits (IC) chip technology depends critically upon the reduction of the interconnects RC delay time. This calls for the development of new low dielectric constant (low-k) insulators, and for work on their integration with lower resistivity copper metallization.A porous silica based film prepared by surfactant templated self-assembly spin-on deposition (SOD) is an attractive candidate as a low-k material. In this research we have studied the structure, chemical composition and bonding of the film and its interface with copper metallization. The decomposition and vaporization of the surfactant in the last step of film deposition resulted in a film with an amorphous structure, as determined by XRD and TEM analysis. Its high porosity (35-58%) was confirmed by XRR and RBS measurements. XPS analysis of the Si2p transition indicated three types of bonding: Si-O, O-Si-C and Si-C. The bonding characteristics were also investigated by FTIR analysis. The effect of a hydrogen plasma post-treatment process on the film topography and bonding was determined by AFM and XPS, respectively. It was found that direct H2 plasma exposure significantly affected the surface roughness of the film and type of chemical bonding. The structure and properties of various PECVD deposited capping layers were also studied, as was the interface between the porous dielectric and Ta, TaxN and Cu (PVD deposited films) after annealing at 200-700°C in vacuum environment for 30 min. At temperatures up to 500°C, no significant diffusion of Cu or Ta into the porous film was detected, as determined by RBS. No copper penetration was detected up to 700°C, according to AES and SIMS analysis. However, at 700°C copper dewetting occurred when it was deposited directly on the porous silica based film.

C4 EM and CPI Reliability Benefits and Process Challenges of FBEOL Integration Changes Implemented in Lead-free C4 Products

2015 ◽  
Vol 2015 (1) ◽  
pp. 000787-000792
Author(s):  
E. Misra ◽  
T. Wassick ◽  
I. Melville ◽  
K. Tunga ◽  
D. Questad ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flip Chip ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Lead Free ◽  
Solder Interconnects ◽  
Design Changes ◽  
Modeling Data ◽  
Free Solder ◽  
Low K

The introduction of low-k & ultra-low-k dielectrics, lead-free (Pb-free) solder interconnects or C4's, and organic flip-chip laminates for integrated circuits have led to some major reliability challenges for the semiconductor industry. These include C4 electromigration (EM) and mechanical failures induced with-in the Si chip due to chip-package interactions (CPI). In 32nm technology, certain novel design changes were evaluated in the last Cu wiring level and the Far Back End of Line levels (FBEOL) to strategically re-distribute the current more uniformly through the Pb-free C4 bumps and therefore improve the C4 EM capabilities of the technology. FBEOL process integration changes, such as increasing the thickness of the hard dielectric (SiNx & SiOx) and reducing the final via diameter, were also evaluated for reducing the mechanical stresses in the weaker BEOL levels and mitigating potential risks for mechanical failures within the Si chip. The supporting white-bump, C4 EM and electrical/mechanical modeling data that demonstrates the benefits of the design and integration changes will be discussed in detail in the paper. Some of the key processing and integration challenges observed due to the design and process updates and the corresponding mitigation steps taken will also be discussed.

Reliability analysis method for low-k interconnect dielectrics breakdown in integrated circuits

2005 ◽  
Vol 98 (3) ◽  
pp. 034503 ◽  
Author(s):  
Gaddi S. Haase ◽  
Ennis T. Ogawa ◽  
Joe W. McPherson
Keyword(s):  
Integrated Circuits ◽  
Reliability Analysis ◽  
Analysis Method ◽  
Low K

Copper Ion Drift Rates in Porous Methylsilsesquiazane Dielectric Films

2000 ◽  
Author(s):  
S. Mukaigawa ◽  
T. Oda ◽  
T. Aoki ◽  
Y. Shimizu ◽  
T. Kikkawa
Keyword(s):  
Copper Ion ◽  
Dielectric Films ◽  
Ion Drift

Observation of space charge limited current by Cu ion drift in porous low-k/Cu interconnects

2010 ◽  
Vol 96 (9) ◽  
pp. 091903 ◽  
Author(s):  
L. S. Chen ◽  
W. H. Bang ◽  
Young-Joon Park ◽  
E. Todd Ryan ◽  
Sean King ◽  
...  
Keyword(s):  
Space Charge ◽  
Space Charge Limited Current ◽  
Cu Interconnects ◽  
Ion Drift ◽  
Limited Current ◽  
Low K ◽  
Space Charge Limited

scholarly journals Spatial behaviour of thermoelasticity with microtemperatures and microconcentrations

2020 ◽  
Vol 34 ◽  
pp. 02001
Author(s):  
Adina Chirilă ◽  
Marin Marin
Keyword(s):  
Mathematical Model ◽  
Partial Differential Equations ◽  
Integrated Circuits ◽  
Boundary Conditions ◽  
Chemical Potential ◽  
Lateral Boundary ◽  
Spatial Behaviour ◽  
Cross Sectional ◽  
Lateral Boundary Conditions ◽  
The Mathematical Model

We consider a thermoelastic material with microtemperatures and microconcentrations. The mathematical model is represented by a system of partial differential equations with the coupling of the displacement, temperature, chemical potential, microconcentrations and microtemperatures fields. The processes of heat and mass diffusion play an important role in many engineering applications, such as satellite problems, manufacturing of integrated circuits or oil extractions. We study the spatial behaviour in a prismatic cylinder occupied by an anisotropic and inhomogeneous material. We impose final prescribed data that are proportional, but not identical, to their initial values. Moreover, we have zero body forces and zero lateral boundary conditions. The spatial behaviour is analysed in terms of some cross-sectional integrals of the solution that depend on the axial variable.

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