Suppression of Schottky leakage current in island-in amorphous silicon thin film transistors with the Cu∕CuMg as source/drain metal

2007 ◽  
Vol 91 (6) ◽  
pp. 062103 ◽  
Author(s):  
M. C. Wang ◽  
T. C. Chang ◽  
Po-Tsun Liu ◽  
R. W. Xiao ◽  
L. F. Lin ◽  
...  
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Leakage Current ◽  
Thin Film Transistors ◽  
Silicon Thin Film

Effects of Mechanical Strain on Amorphous Silicon Thin-Film Transistors

2002 ◽  
Vol 715 ◽  
Author(s):  
H. Gleskova ◽  
S. Wagner ◽  
W. Soboyejo ◽  
Z. Suo
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Leakage Current ◽  
Thin Film Transistors ◽  
Tensile Strain ◽  
Mechanical Strain ◽  
Positive Sign ◽  
Silicon Thin Film ◽  
Polyimide Foil

AbstractWe evaluated a-Si:H TFTs fabricated on polyimide foil under uniaxial compressive or tensile strain. The strain was induced by bending or stretching. All experiments confirmed that the on-current and hence the electron linear mobility depend on strain å as μ = μ0 (1 + 26·ε), where tensile strain has a positive sign. Upon the application of stress the mobility changes instantly and then remains unchanged in measurements up to 40 hours. In the majority of the TFTs the off-current and leakage current do not change. In tension, the TFTs fail mechanically at a strain of ∼ 3x10-2 but recover if the strain is released ‘immediately’.

Characterization of Photo Leakage Current of Amorphous Silicon Thin-Film Transistors

1999 ◽  
Vol 38 (Part 1, No. 11) ◽  
pp. 6202-6206 ◽  
Author(s):  
Yoshimi Yamaji ◽  
Mitsushi Ikeda ◽  
Masahiko Akiyama ◽  
Takahiko Endo
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Leakage Current ◽  
Thin Film Transistors ◽  
Silicon Thin Film

Studies of the Stability of Amorphous Silicon Thin Film Transistors

1992 ◽  
Vol 258 ◽  
Author(s):  
T. Globus ◽  
M. Shur ◽  
M. Hack
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Leakage Current ◽  
Thin Film Transistors ◽  
Experimental Studies ◽  
Gate Insulator ◽  
Localized States ◽  
Silicon Thin Film ◽  
Insulator Layer ◽  
Voltage Stress

ABSTRACTOur experimental studies confirm that changes in a-Si Thin Film Transistors (TFTs) under voltage stress occur in the device channel and not in the contacts. We demonstrate that stressing an a-Si TFT not only shifts the device threshold voltage but can also changes the slope of the semilog subthreshold current dependence on the gate voltage. In addition, stressing can decrease the minimum leakage current. The creation of new localized states in the amorphous silicon under voltage stress qualitatively explains all these effects, while carrier tunneling and trapping in the gate insulator layer cannot by itself explain our data. At large negative gate voltages, the leakage current increases due to the holes injected into the channel. This hole current is also affected by voltage stress as can be predicted by the state creation mechanism.

The Instability Characteristics of Amorphous Silicon Thin Film Transistors with Various Interfacial and Bulk Defect States

1997 ◽  
Vol 36 (Part 1, No. 10) ◽  
pp. 6226-6229 ◽  
Author(s):  
Huang-Chung Cheng ◽  
Jun-Wei Tsai ◽  
Chun-Yao Huang ◽  
Fang-Chen Luo ◽  
Hsing-Chien Tuan
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Defect States ◽  
Silicon Thin Film

Hot-Wire Deposited Amorphous Silicon Thin-Film Transistors

1996 ◽  
Vol 424 ◽  
Author(s):  
R. E. I. Schropp ◽  
K. F. Feenstra ◽  
C. H. M. Van Der Werf ◽  
J. Holleman ◽  
H. Meiling
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Chemical Vapor ◽  
Current Crowding ◽  
Hot Wire ◽  
Saturation Regime ◽  
Silicon Thin Film ◽  
Order Of Magnitude

AbstractWe present the first thin film transistors (TFTs) incorporating a low hydrogen content (5 - 9 at.-%) amorphous silicon (a-Si:H) layer deposited by the Hot-Wire Chemical Vapor Deposition (HWCVD) technique. This demonstrates the possibility of utilizing this material in devices. The deposition rate by Hot-Wire CVD is an order of magnitude higher than by Plasma Enhanced CVD. The switching ratio for TFTs based on HWCVD a-Si:H is better than 5 orders of magnitude. The field-effect mobility as determined from the saturation regime of the transfer characteristics is still quite poor. The interface with the gate dielectric needs further optimization. Current crowding effects, however, could be completely eliminated by a H2 plasma treatment of the HW-deposited intrinsic layer. In contrast to the PECVD reference device, the HWCVD device appears to be almost unsensitive to bias voltage stressing. This shows that HW-deposited material might be an approach to much more stable devices.

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