High-speed GaAs metal gate semiconductor field effect transistor structure grown on a composite Ge∕GexSi1−x∕Si substrate

2007 ◽  
Vol 101 (8) ◽  
pp. 084501 ◽  
Author(s):  
Guang-Li Luo ◽  
Yen-Chang Hsieh ◽  
Edward Yi Chang ◽  
M. H. Pilkuhn ◽  
Chao-Hsin Chien ◽  
...  
Keyword(s):  
Field Effect ◽  
High Speed ◽  
Field Effect Transistor ◽  
Si Substrate ◽  
Metal Gate ◽  
Transistor Structure ◽  
Effect Transistor

Short-Channel Tunneling Field-Effect Transistor with Drain-Overlap and Dual-Metal Gate Structure for Low-Power and High-Speed Operations

2015 ◽  
Vol 15 (10) ◽  
pp. 7430-7435 ◽  
Author(s):  
Young Jun Yoon ◽  
Hye Rim Eun ◽  
Jae Hwa Seo ◽  
Hee-Sung Kang ◽  
Seong Min Lee ◽  
...  
Keyword(s):  
Low Power ◽  
Field Effect ◽  
High Speed ◽  
Field Effect Transistor ◽  
Tunneling Current ◽  
Metal Gate ◽  
Short Channel ◽  
Gate Structure ◽  
Effect Transistor ◽  
Dual Metal

We have investigated and proposed a highly scaled tunneling field-effect transistor (TFET) based on Ge/GaAs heterojunction with a drain overlap to suppress drain-induced barrier thinning (DIBT) and improve low-power (LP) performance. The highly scaled TFET with a drain overlap achieves lower leakage tunneling current because of the decrease in tunneling events between the source and drain, whereas a typical short-channel TFET suffers from a great deal of tunneling leakage current due to the DIBT at the off-state. However, the drain overlap inevitably increases the gate-to-drain capacitance (Cgd) because of the increase in the overlap capacitance (Cov) and inversion capacitance (Cinv). Thus, in this work, a dual-metal gate structure is additionally applied along with the drain overlap. The current performance and the total gate capacitance (Cgg) of the device with a dual-metal gate can be possibly controlled by adjusting the metal gate workfunction (Φgate) and Φoverlap-gate in the overlapping regions. As a result, the intrinsic delay time (τ) is greatly reduced by obtaining lower Cgg divided by the on-state current (Ion), i.e., Cgg/Ion. We have successfully demonstrated excellent LP and high-speed performance of a highly scaled TFET by adopting both drain overlap and dual-metal gate with DIBT minimization.

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