Thin films of high-k material are becoming more and more used for semiconductor devices. A further shrinking of the devices requires also a further reduction of the high-k film thickness. With this reduction of the high-k thickness down to just a few nanometers two technical challenges have to be addressed. The first one is the ALD process for the deposition of the high-k material. Usually the ALD process can be well controlled by tuning the number of process cycles. But it is theoretically predicted [1] that the growth-per-cycle of the first cycles can be different than the steady growth-per-cycle which is obtained for high cycle numbers. This effect is caused by a not fully covered initial surface during the first cycles. Only when the deposited material forms a closed surface and the surface probabilities are the same for each following cycle the deposition rate will be constant. The second challenge is that the electrical properties of thin films with a thickness of a few nanometers are significantly determined by the quality of the interface between the film and the substrate.