Direct correlation between microstructure and mechanical tensile properties in Pb-free solders and eutectic SnPb solder for flip chip technology

2001 ◽  
Vol 79 (4) ◽  
pp. 482-484 ◽  
Author(s):  
J. W. Jang ◽  
A. P. De Silva ◽  
T. Y. Lee ◽  
J. K. Lin ◽  
D. R. Frear
Keyword(s):  
Tensile Properties ◽  
Flip Chip ◽  
Chip Technology ◽  
Snpb Solder ◽  
Mechanical Tensile ◽  
Eutectic Snpb

Self-Aligned Hermetic Packaging Using Eutectic SnPb Solder and Cr/Ni/Cu Metallization Layer

2004 ◽  
Author(s):  
Annie T. Huang ◽  
Chung-Kuang Chou ◽  
Chih Chen
Keyword(s):  
Flip Chip ◽  
Hot Plate ◽  
Hermetic Packaging ◽  
Chip Technology ◽  
Snpb Solder ◽  
Localized Heating ◽  
Circle Patterns ◽  
Silicon Silicon ◽  
Heating Technology ◽  
Eutectic Snpb

This paper reports an easy, low cost, and low temperature hermetic packaging technology utilizing eutectic SnPb solder and Cr/Ni/Cu bonding pad. We investigate the bonding results of silicon-silicon as well as silicon-glass and glass-glass bonding. Most hermetic packaging technologies require a bonding temperature higher than 300°C. Because some devices are sensitive to temperature that decreases their functionalities, two localized heating technology have been proposed. One technology generates heat via built-in-microheaters on the silicon substrate. Another localized heating technology utilizes microwave as a heating source [1]. However, both technologies require high cost and cannot be implemented for mass production. Furthermore, local heating creates a large temperature gradient. The stress causes crack on the substrates, thus limiting the selection of substrate materials. We choose eutectic tin-lead with the melting temperature of 183°C. Metal thin films we choose is also similar to the under bump metallurgy used for flip chip technology. The advantage of solder is its metal property. With a width of a few micrometers, metal can block moisture for over a decade. In addition, solder is known to pertain self-aligning property in flip chip technology. Other kind of solders can also be applied for hermetic packaging as well. Shie et al have tested In-Sn as bonding using the reflow temperature as low as 120 °C [2]. Seong-A Kim et. al have tested Au-Sn solder line at 400°C [3,4]. Due to the difference in melting points, the application of Sn-Pb, Au-Sn and In-Sn can be different. Bonding characteristic of our design is investigated on three different setups: silicon-silicon, silicon-glass, and glass-glass samples. (Fig.1) This experiment consists of three different setups: silicon-to-silicon bonding, silicon-to-glass bonding, and glass-to-glass bonding. These three different setups utilize the same bonding method. The design includes square patterns and circle patterns of 500 μm width as shown in Figure 2. Schematic process flow of sample fabrication is demonstrated in Figure 3. Substrate and cap have identical size with the pattern of square of 1 cm in width or circle of 1 cm in diameter. The bonding pad is composed of three layers of metal from bottom to top: 500 Å of chromium, 2000 Å of nickel and 6000 Å of copper.(Fig.3b) Eutectic SnPb solder is reflowed on square or circle patterns on a hot plate at room ambient.(Fig.3d) Sample pairs are then bonded on a hot plate at 200°C for about 1.5 minutes for silicon-silicon and silicon glass bonding and 3 minutes for glass-glass bonding.(Fig.3e) Before placing the sample pairs on the hot plate, for glass-glass and glass-silicon bonding, we align a pair of chips of matched pattern by visual alignment. For silicon-silicon bonding, we align two chips along the dividing lines. Figure 4a and 4b show a glass and a silicon sample after solder reflow respectively. Sample pairs after bonding process are seen in Figure 5a through 5c. Figures 6a through 6c show the cross-sectional picture of the joint. Figures 6b and 6c are enlarged pictures of left and right side of the joints respectively. The average misalignment is 11.2 μm and 13.6 μm for square and circle samples respectively. Bonding strength of the three setups ranges from 3 MPa to 10 MPa. For leakage rate test, a 3 mm hole in diameter was drilled under the sealed area on the substrate side, followed by connecting a glass pipe to the hole by frit glass. The setup can be pumped down to the order of 10−8 torr.

Electromigration of eutectic SnPb solder interconnects for flip chip technology

2001 ◽  
Vol 89 (6) ◽  
pp. 3189-3194 ◽  
Author(s):  
T. Y. Lee ◽  
K. N. Tu ◽  
S. M. Kuo ◽  
D. R. Frear
Keyword(s):  
Flip Chip ◽  
Solder Interconnects ◽  
Chip Technology ◽  
Snpb Solder ◽  
Eutectic Snpb

scholarly journals Cross interactions on interfacial compound formation of solder bumps and metallization layers during reflow

2004 ◽  
Vol 19 (12) ◽  
pp. 3654-3664 ◽  
Author(s):  
T.L. Shao ◽  
T.S. Chen ◽  
Y.M. Huang ◽  
Chih Chen
Keyword(s):  
Flip Chip ◽  
Driving Forces ◽  
The Other ◽  
Compound Formation ◽  
Bump Height ◽  
Performance Requirements ◽  
Substrate Side ◽  
Solder Bumps ◽  
Snpb Solder ◽  
Eutectic Snpb

While the dimension of solder bumps keeps shrinking to meet higher performance requirements, the formation of interfacial compounds may be affected more profoundly by the other side of metallization layer due to a smaller bump height. In this study, cross interactions on the formation of intermetallic compounds (IMCs) were investigated in eutectic SnPb, SnAg3.5, SnAg3.8Cu0.7, and SnSb5 solders jointed to Cu/Cr–Cu/Ti on the chip side and Au/Ni metallization on the substrate side. It is found that the Cu atoms on the chip side diffused to the substrate side to form (Cux,Ni1−x)6Sn5 or (Niy,Cu1−y)3Sn4 for the four solders during the reflow for joining flip chip packages. For the SnPb solder, Au atoms were observed on the chip side after the reflow, yet few Ni atoms were detected on the chip side. In addition, for SnAg3.5 and SnSn5 solders, the Ni atoms on the substrate side migrated to the chip side during the reflow to change binary Cu6Sn5 into ternary (Cux,Ni1−x)6Sn5 IMCs, in which the Ni weighed approximately 21%. Furthermore, it is intriguing that no Ni atoms were detected on the chip side of the SnAg3.8Cu0.7 joint. The possible driving forces responsible for the diffusion of Au, Ni, and Cu atoms are discussed in this paper.

Measurement of electromigration activation energy in eutectic SnPb and SnAg flip-chip solder joints with Cu and Ni under-bump metallization

2010 ◽  
Vol 25 (9) ◽  
pp. 1847-1853 ◽  
Author(s):  
Hsiao-Yun Chen ◽  
Chih Chen
Keyword(s):  
Activation Energy ◽  
Flip Chip ◽  
Void Formation ◽  
Under Bump Metallization ◽  
Solder Bumps ◽  
Snpb Solder ◽  
Snag Solder ◽  
Temperature Coefficient Of Resistivity ◽  
Eutectic Snpb ◽  
Real Temperature

Electromigration activation energy is measured by a built-in sensor that detects the real temperature during current stressing. Activation energy can be accurately determined by calibrating the temperature using the temperature coefficient of resistivity of an Al trace. The activation energies for eutectic SnAg and SnPb solder bumps are measured on Cu under-bump metallization (UBM) as 1.06 and 0.87 eV, respectively. The activation energy mainly depends on the formation of Cu–Sn intermetallic compounds. On the other hand, the activation energy for eutectic SnAg solder bumps with Cu–Ni UBM is measured as 0.84 eV, which is mainly related to void formation in the solder.

Effects of substrate metallizations on solder/underbump metallization interfacial reactions in flip-chip packages during thermal aging

2003 ◽  
Vol 18 (6) ◽  
pp. 1333-1341 ◽  
Author(s):  
F. Zhang ◽  
M. Li ◽  
C. C. Chum ◽  
C-H. Tung
Keyword(s):  
Porous Structure ◽  
Thermal Aging ◽  
Flip Chip ◽  
Interfacial Reactions ◽  
Snagcu Solder ◽  
Solution Type ◽  
Snpb Solder ◽  
Underbump Metallization ◽  
Eutectic Snpb

Effects of Ni and Au from Ni/Au substrate metallizations on the interfacial reactions of solder joints in flip-chip packages during long-term thermal aging were systematically investigated. It was found that both Au and Ni influenced the solid-state interfacial reactions, underbump metallization (UBM), and intermetallic compound (IMC) evolution. Because large amounts of Ni could incorporate into IMC to form a multicomponent (Cu, Ni)6Sn5 phase during assembly reflow, while Au could only affect the reaction during thermal aging through the reconfiguration of AuSn4 phase, Ni had stronger effects on solid-solution type Ni–V UBM consumption than Au. It was found that the UBM consumption process was faster in the eutectic SnPb solder system than that in the SnAgCu solder system during aging. A porous structure was formed in the UBM layer after Ni in UBM was consumed. Electrical resistance of flip-chip packages increased significantly after the porous structure reached certain extents. The results showed that the diffusion process of Ni from UBM and Sn from solder in the presence of (Cu, Ni)6Sn5 or (Ni, Cu)3Sn4 phase at solder joint interfaces could be much faster than that in the case of binary Cu6Sn5 or Ni3Sn4 IMC.

Thin-Die Flip Chip Physical-FA Process Flow

2002 ◽  
Author(s):  
Andrew J. Komrowski ◽  
N. S. Somcio ◽  
Daniel J. D. Sullivan ◽  
Charles R. Silvis ◽  
Luis Curiel ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Preparation Methods ◽  
Chip Technology ◽  
Isolation Test ◽  
Sample Preparation Methods

Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.

Failure Analysis of Flip-Chip Interconnections Through Acoustic Microscopy

1996 ◽  
Author(s):  
O. Diaz de Leon ◽  
M. Nassirian ◽  
C. Todd ◽  
R. Chowdhury
Keyword(s):  
Failure Analysis ◽  
Large Scale ◽  
Flip Chip ◽  
Ultrasonic Waves ◽  
Acoustic Microscopy ◽  
Acoustic Microscope ◽  
Chip Technology ◽  
Ball Joints ◽  
Non Destructive ◽  
Scanning Acoustic Microscope

Abstract Integration of circuits on semiconductor devices with resulting increase in pin counts is driving the need for improvements in packaging for functionality and reliability. One solution to this demand is the Flip- Chip concept in Ultra Large Scale Integration (ULSI) applications [1]. The flip-chip technology is based on the direct attach principle of die to substrate interconnection.. The absence of bondwires clearly enables packages to become more slim and compact, and also provides higher pin counts and higher-speeds [2]. However, due to its construction, with inherent hidden structures the Flip-Chip technology presents a challenge for non-destructive Failure Analysis (F/A). The scanning acoustic microscope (SAM) has recently emerged as a valuable evaluation tool for this purpose [3]. C-mode scanning acoustic microscope (C-SAM), has the ability to demonstrate non-destructive package analysis while imaging the internal features of this package. Ultrasonic waves are very sensitive, particularly when they encounter density variations at surfaces, e.g. variations such as voids or delaminations similar to air gaps. These two anomalies are common to flip-chips. The primary issue with this package technology is the non-uniformity of the die attach through solder ball joints and epoxy underfill. The ball joints also present defects as open contacts, voids or cracks. In our acoustic microscopy study packages with known defects are considered. It includes C-SCAN analysis giving top views at a particular package interface and a B-SCAN analysis that provides cross-sectional views at a desired point of interest. The cross-section analysis capability gives confidence to the failure analyst in obtaining information from a failing area without physically sectioning the sample and destroying its electrical integrity. Our results presented here prove that appropriate selection of acoustic scanning modes and frequency parameters leads to good reliable correlation between the physical defects in the devices and the information given by the acoustic microscope.

scholarly journals Design and Switching Characteristics of Flip-Chip GaN Half-Bridge Modules Integrated with Drivers

2021 ◽  
Vol 11 (15) ◽  
pp. 7057
Author(s):  
Lin Wang ◽  
Zhe Cheng ◽  
Zhi-Guo Yu ◽  
De-Feng Lin ◽  
Zhe Liu ◽  
...  
Keyword(s):  
Flip Chip ◽  
High Electron Mobility Transistors ◽  
Wire Bonding ◽  
High Electron ◽  
Parasitic Inductance ◽  
Switching Performance ◽  
Turn On ◽  
Electron Mobility Transistors ◽  
Chip Technology ◽  
Switching Characteristics

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.

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