A high‐speed wide dynamic range time‐to‐digital converter

1994 ◽  
Vol 65 (11) ◽  
pp. 3577-3584 ◽  
Author(s):  
M. Lampton ◽  
R. Raffanti
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Digital Converter ◽  
Wide Dynamic Range ◽  
Time To Digital Converter

A Low-Power High-Linear Time-to-Digital Converter for Measuring R-R Intervals in ECG Signal Optimized by Neural Network and TLBO Algorithm

2018 ◽  
Vol 28 (02) ◽  
pp. 1950021
Author(s):  
B. Ghanavati ◽  
E. Abiri ◽  
M. R. Salehi ◽  
N. Azhdari
Keyword(s):  
Neural Network ◽  
Dynamic Range ◽  
Linear Time ◽  
Optimization Method ◽  
Cmos Technology ◽  
Time Interval ◽  
Digital Converter ◽  
Two Stage ◽  
Time To Digital Converter ◽  
Tlbo Algorithm

In this paper, a two-stage time interpolation time-to-digital converter (TDC) is proposed to achieve adequate resolution and wide dynamic range for measuring R-R intervals in QRS detection. The architecture is based on a coarse counter and a couple of two-stage interpolator circuit in order to improve the conversion linearity. The proposed TDC is modeled with the neural network, while the teacher–learner-based optimization algorithm (TLBO) is used to optimize the integral nonlinearity (INL) of the proposed TDC. The proposed optimization method shows a characteristic close to the ideal output of the TDC behavior over a wide input range. Using the achieved results of the TLBO algorithm simulation results using CADENCE VIRTUOSO and standard 180[Formula: see text]nm CMOS technology shows 1.2[Formula: see text]s dynamic range, 100[Formula: see text]ns resolution, 0.19[Formula: see text]mW power consumption and area of 0.16[Formula: see text]mm2. The proposed circuit can find application in biomedical engineering systems and other fields where long and accurate time interval measurement is needed.

scholarly journals Avalanche Photodiodes with Dual Multiplication Layers for High-Speed and Wide Dynamic Range Performances

Photonics ◽  
2021 ◽  
Vol 8 (4) ◽  
pp. 98
Author(s):  
Naseem ◽  
Zohauddin Ahmad ◽  
Yan-Min Liao ◽  
Rui-Lin Chao ◽  
Po-Shun Wang ◽  
...  
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Avalanche Photodiodes ◽  
High Gain ◽  
Absorber Layer ◽  
Light Illumination ◽  
Modulation Amplitude ◽  
Back Side ◽  
Wide Dynamic Range ◽  
Avalanche Process

In this work, we demonstrate In0.52Al0.48As top/backside-illuminated avalanche photodiodes (APD) with dual multiplication layers for high-speed and wide dynamic range performances. Our fabricated top-illuminated APDs, with a partially depleted p-type In0.53Ga0.47As absorber layer and thin In0.52Al0.48As dual multiplication (M-) layer (60 and 88 nm), exhibit a wide optical-to-electrical bandwidth (16 GHz) with high responsivity (2.5 A/W) under strong light illumination (around 1 mW). The measured bias dependent 3-dB O-E bandwidth was pinned at 16 GHz without any serious degradation near the saturation current output. To further increase the speed, we downscaled the active diameter and adopted a back-side illuminated structure with flip-chip bonding for batter optical alignment tolerance. A significant improvement in maximum bandwidth was demonstrated (25 versus 18 GHz). On the other hand, we adopted a thick dual M-layer (200 and 300 nm) and 2 μm absorber layer in the APD design to circumvent the problem of serious bandwidth degradation under high gain (>100) and high-power operation which significantly enhanced the dynamic range. Due to dual M-layer, the carriers could be energized in the first M-layer then propagate to the second M-layer to trigger the avalanche process. In both cases, despite variation in thickness of the absorber and M-layer, the cascade avalanche process leads to values close to the ultra-high gain bandwidth product (GBP) of around 460 GHz with a responsivity of 0.4 and 1 A/W at unit gain for the thin and thick M-layer devices, respectively. We successfully achieved a good sensitivity of around −20.6 dBm optical modulation amplitude (OMA) at a data rate of 25.78 Gb/s, by packaging the fabricated APDs (thin dual M-layer (60 and 88 nm) version) with a 25 Gb/s trans-impedance amplifier in a 100 Gb/s ROSA package. The results show that, the incorporation of a dual multiplication (M) layer structure in the APD opens a new window to obtaining the higher GBP in order to meet the requirements for high-speed transmission without the need of further downscaling the multiplication layer.

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