Criterion for blocking threading dislocations by strained buffer layers in GaAs grown on Si substrates

1989 ◽  
Vol 55 (20) ◽  
pp. 2096-2098 ◽  
Author(s):  
N. A. El‐Masry ◽  
J. C. L. Tarn ◽  
S. Hussien
Keyword(s):  
Buffer Layers ◽  
Threading Dislocations ◽  
Si Substrates

Defect Reduction in GaAs Epilayers on Si Substrates Using Strained Layer Superlattices

1987 ◽  
Vol 91 ◽  
Author(s):  
N. El-Masry ◽  
N. Hamaguchi ◽  
J.C.L. Tarn ◽  
N. Karam ◽  
T.P. Humphreys ◽  
...  
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Buffer Layers ◽  
Threading Dislocations ◽  
Defect Reduction ◽  
Strained Layer ◽  
Si Substrates ◽  
Density Of Dislocations ◽  
Strained Layer Superlattice ◽  
Strained Layer Superlattices

ABSTRACTInxGa11-xAs-GaAsl-yPy strained layer superlattice buffer layers have been used to reduce threading dislocations in GaAs grown on Si substrates. However, for an initially high density of dislocations, the strained layer superlattice is not an effective filtering system. Consequently, the emergence of dislocations from the SLS propagate upwards into the GaAs epilayer. However, by employing thermal annealing or rapid thermal annealing, the number of dislocation impinging on the SLS can be significantly reduced. Indeed, this treatment greatly enhances the efficiency and usefulness of the SLS in reducing the number of threading dislocations.

scholarly journals Evolution of Threading Dislocations in GaN Films Grown on (111) Si Substrates with Various Buffer Layers

2006 ◽  
Vol 12 (S02) ◽  
pp. 906-907
Author(s):  
X Weng ◽  
J Acord ◽  
A Jain ◽  
S Raghavan ◽  
J Redwing ◽  
...  
Keyword(s):  
Buffer Layers ◽  
Threading Dislocations ◽  
Si Substrates

Extended abstract of a paper presented at Microscopy and Microanalysis 2006 in Chicago, Illinois, USA, July 30 – August 3, 2006

Anisotropy of interfacial defects in the initial stage of MOVPE GaAs growth On Si

1990 ◽  
Vol 48 (4) ◽  
pp. 592-593
Author(s):  
C. Vannuffel ◽  
C. Schiller ◽  
J. P. Chevalier
Keyword(s):  
Early Stage ◽  
Threading Dislocations ◽  
Mbe Growth ◽  
Detailed Mechanism ◽  
Si Substrates ◽  
Initial Stage ◽  
Interfacial Defects ◽  
Interfacial Dislocations ◽  
Step Growth ◽  
Essential Problem

Recently, interest has focused on the epitaxy of GaAs on Si as a promising material for electronic applications, potentially for integration of optoelectronic devices on silicon wafers. The essential problem concerns the 4% misfit between the two materials, and this must be accommodated by a network of interfacial dislocations with the lowest number of threading dislocations. It is thus important to understand the detailed mechanism of the formation of this network, in order to eventually reduce the dislocation density at the top of the layers.MOVPE growth is carried out on slightly misoriented, (3.5°) from (001) towards , Si substrates. Here we report on the effect of this misorientation on the interfacial defects, at a very early stage of growth. Only the first stage, of the well-known two step growth process, is thus considered. Previously, we showed that full substrate coverage occured for GaAs thicknesses of 5 nm in contrast to MBE growth, where substantially greater thicknesses are required.

Effects of the Sputtering Time of AlN Buffer Layer on the Quality of ZnO Thin Films

2014 ◽  
Vol 881-883 ◽  
pp. 1117-1121 ◽  
Author(s):  
Xiang Min Zhao
Keyword(s):  
Thin Films ◽  
Buffer Layer ◽  
Rf Magnetron Sputtering ◽  
Buffer Layers ◽  
Zno Thin Films ◽  
Zno Films ◽  
Si Substrates ◽  
Atomic Force ◽  
Structure Morphology ◽  
Aln Buffer

ZnO thin films with different thickness (the sputtering time of AlN buffer layers was 0 min, 30 min,60 min, and 90 min, respectively) were prepared on Si substrates using radio frequency (RF) magnetron sputtering system.X-ray diffraction (XRD), atomic force microscope (AFM), Hall measurements setup (Hall) were used to analyze the structure, morphology and electrical properties of ZnO films.The results show that growth are still preferred (002) orientation of ZnO thin films with different sputtering time of AlN buffer layer,and for the better growth of ZnO films, the optimal sputtering time is 60 min.

Short-period (Si14 / Si0.75 Ge0.25)20 Superlattices for the Growth of High-quality Si0.75 Ge0.25

2003 ◽  
Vol 765 ◽  
Author(s):  
M.M. Rahman ◽  
T. Tambo ◽  
C. Tatsuyama
Keyword(s):  
Low Temperature ◽  
Alloy Layer ◽  
Buffer Layers ◽  
Threading Dislocations ◽  
Strained Layers ◽  
Temperature Growth ◽  
Low Temperature Growth ◽  
Defect Sites ◽  
Short Period ◽  
Different Temperatures

AbstractIn the present experiment, we have grown 2500-Å thick Si0.75Ge0.25 alloy layers on Si(001) substrate by MBE process using a short-period (Si14/Si0.75Ge0.25)20 superlattice (SL) as buffer layers. In the SL layers, first a layer of 14 monolayers (MLs) of Si (thickness about 20Å) then a thin layer of Si0.75Ge0.25 (thickness 5-6Å) were grown. This Si/(Si0.75Ge0.25) bilayers were repeated for 20 times. The buffer layers were grown at different temperatures from 300-400°C and the alloy layers were then grown at 500°C on the buffer layers. The alloy layer showed low residual strain (about -0.16%) and smooth surface (rms roughness ~15Å) with 300°C grown SL buffer. Low temperature growth of Si in SL layer introduces point defects and low temperature growth of Si1-xGex in SL layer reduces the Ge segregation length, which leads to strained SL layer formation. Strained layers are capable to make barrier for the propagation of threading dislocations and point defect sites can trap the dislocations.

Monolithic integration of room-temperature cw GaAs/AlGaAs lasers on Si substrates via relaxed graded GeSi buffer layers

2003 ◽  
Vol 93 (1) ◽  
pp. 362-367 ◽  
Author(s):  
Michael E. Groenert ◽  
Christopher W. Leitz ◽  
Arthur J. Pitera ◽  
Vicky Yang ◽  
Harry Lee ◽  
...  
Keyword(s):  
Room Temperature ◽  
Monolithic Integration ◽  
Buffer Layers ◽  
Si Substrates

MBE Growth of Low Dislocation and High Mobility GaAs-on-Si

1986 ◽  
Vol 67 ◽  
Author(s):  
Jhang Woo Lee
Keyword(s):  
Layer Structure ◽  
High Mobility ◽  
Gaas Layer ◽  
Buffer Layers ◽  
Misfit Dislocations ◽  
Si Substrates ◽  
Molecular Beam Epitaxial ◽  
Transmission Electron ◽  
Low Dislocation Density ◽  
Molecular Beam Epitaxial Growth

ABSTRACTData is presented on the optimization of several molecular beam epitaxial growth processes to provide low dislocation density and high mobility GaAs single crystals on (100) Si wafers. The substrate tilt angle, the growth temperature, and the first buffer layer structure, were investigated Tor this purpose. Using Hall measurements the GaAs layers grown on 2 or 3-degree tilt (100) Si showed consistently high mobilities which are equivalent to the homoepitaxial GaAs mobility. Transmission electron microscopy (TEM) revealed that on tilted (100) Si substrates most of the misfit dislocations were confined within the first 50 Å GaAs layer by forming a type of edge dislocation at the Si surface step edges. Also low temperature grown buffer layers always gave better morphologies and lower etch pit densities while keeping the high mobilities on overgrown GaAs layers.

Observation of GaAs/Si Epitaxial Interfaces by Atomic Resolution Electron Microscopy

1986 ◽  
Vol 67 ◽  
Author(s):  
N. Otsuka ◽  
C. Choi ◽  
Y. Nakamura ◽  
S. Nagakura ◽  
R. Fischer ◽  
...  
Keyword(s):  
Substrate Surface ◽  
High Vacuum ◽  
Ultra High Vacuum ◽  
Threading Dislocations ◽  
Misfit Dislocations ◽  
Si Substrates ◽  
Voltage Electron ◽  
Resolution Electron ◽  
Gaas Films ◽  
Substrate Surfaces

ABSTRACTRecent studies have shown that high quality GaAs films can be grown by MBE on Si substrates whose surfaces are slightly tilted from the (100) plane. In order to investigate the effect of the tilting of substrate surfaces on the formation of threading dislocations, the GaAs/Si epitaxial interfaces have been observed with a 1 MB ultra-high vacuum, high voltage electron microscope. Two types of misfit dislocations, one with Burgers vectors parallel to the interface and the other with Burgers vectors inclined from the interface, were found in these epitaxial interfaces. The observation of crosssectional samples perpendicular to each other has shown that the tilting of the substrate surface directly influences the generation of these two types of misfit dislocations. The mechanism of the reduction of threading dislocations by the tilting of the substrate surface is discussed based on these observations.

Influence of Interface States on Output Characteristics of 4H-SiC MESFETs on Semi–Insulating Substrates

2000 ◽  
Vol 640 ◽  
Author(s):  
Nabil Sghaier ◽  
Abdel K. Souifi ◽  
Jean-Marie Bluet ◽  
Manuel Berenguer ◽  
Gérard Guillot ◽  
...  
Keyword(s):  
Gate Voltage ◽  
Frequency Dispersion ◽  
Buffer Layers ◽  
Si Substrate ◽  
Substrate Interface ◽  
Si Substrates ◽  
Kink Effect ◽  
Parasitic Effect ◽  
Output Characteristics ◽  
Output Conductance

ABSTRACTThe aim of this work is to study the origin of parasitic phenomena in the output characteristics of 4H-SiC MESFETs on semi-insulating (SI) substrates with various buffer layers. Ids-Vds measurements as a function of temperature have first been performed. Different parasitic effects such as kink effect, hysteresis effect when the gate voltage is successively increased or decreased, or changes in the output characteristics after a high drain polarization are presented. Random Telegraph Signal (RTS) measurements and frequency dispersion of the output conductance have next been realized. From the obtained results, we propose that the parasitic effect on the output characteristics are correlated with the presence of deep levels located near the semi -insulating substrate interface. The main observed trap is tentatively attributed to the presence of Vanadium in the SI substrate.

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