Practical equalization and synchronization strategies for use in serial data transmission over h.f. channels

1983 ◽  
Vol 53 (4) ◽  
pp. 141 ◽  
Author(s):  
W. Hodgkiss ◽  
L.F. Turner
Keyword(s):  
Data Transmission ◽  
Serial Data

High-Speed Serial Data Transmission Error Control Based on Fuzzy Classification

2018 ◽  
Vol 22 (7) ◽  
pp. 1077-1081
Author(s):  
Zhimin Zhang ◽  
Keyword(s):  
Energy Consumption ◽  
Packet Loss ◽  
Data Transmission ◽  
High Speed ◽  
Error Control ◽  
Transmission Error ◽  
Fuzzy Classification ◽  
Control Data ◽  
Transmission Errors ◽  
Serial Data

At present, the error control method for high-speed serial data transmission obtains the errors by comparison and then controls them. If the data transmission channel is not denoised, the packet loss and error codes become serious, and energy consumption increases. The use of fuzzy classification is proposed to control data transmission errors. The method uses the combination of wavelet transform and transform domain difference to double denoise the channel, and it completes the clustering of data transmission errors by fuzzy classification. Considering packet loss, error codes, and energy consumption in data transmission error control, when the communication distance between two nodes is small, automatic repeat request is used to control data transmission errors. As the distance between nodes increases, forward error correction is used to control data transmission errors. When the communication distance gradually increases, data transmission errors are controlled by hybrid automatic repeat request. Experiments showed that the proposed method can reduce the data transmission error, control energy consumption, packet loss rate, and bit error rate, and enhance the denoising effect.

scholarly journals Low-power, low-latency transceiver design using d-TGMS flip-flop for on-chip interconnects

2018 ◽  
Vol 7 (1) ◽  
pp. 106
Author(s):  
U. Saravanakumar ◽  
P Suresh ◽  
S.P Vimal
Keyword(s):  
Low Power ◽  
Data Transmission ◽  
Power Reduction ◽  
Decision Feedback ◽  
Phase Locked Loops ◽  
Nand Gate ◽  
Flip Flop ◽  
Processing Elements ◽  
Serial Data ◽  
On Chip

The routers in Network on Chips (NoCs) are used to transmit the data among the Processing Elements (PEs) in the field, and it can be done through transmission links between the routers. Traditionally, the data transmission between the PEs of NoC is carried out by the parallel bus which consumes more power, leads to be complex routing strategies and occupies more area within the field. Instead of parallel bus, serializes and deserialisers are used for serial data transmission, which consumes very less power and area than traditional method. To implement serialiser-deserialiser at the transceiver in the router for on chip communication, a three-level encoding technique is implemented in this design, which eliminates power hungry blocks in earlier works, such as Phase Locked Loops, Feed Forward Equalizers, Decision Feedback Equalizers and the repeaters along the transmission line. In this paper, a low-power transceiver is proposed using modified C2MOS flip flop and Dynamic TGMS flip flop circuits in order to minimize the delay. The power reduction of 35.683% and the delay reduction of 44.71% were achieved in the proposed transceiver than the NAND gate based D flip flop transceivers.

scholarly journals A new digital attenuator system for hybrid computers

SIMULATION ◽  
1967 ◽  
Vol 8 (4) ◽  
pp. 227-235 ◽  
Author(s):  
Conrad Paul Pracht
Keyword(s):  
Data Transmission ◽  
Metal Film ◽  
Control Logic ◽  
Digital To Analog Converters ◽  
System A ◽  
Serial Data ◽  
Contact Life ◽  
Hybrid Computer ◽  
Address Line ◽  
Maximum Contact

Digital attenuators are simple multiplying digital-to-analog converters used to replace coefficient-setting potentiome ters in modern analog/hybrid computers. This report de scribes a new digital attenuator system employing low- phase-shift miniature metal-film ladder networks. They are switched by latching reed relays which give the system a nondestructive coefficient memory even when the com puter is switched off. New digital control logic employs serial data transmission and requires only one address line per 14-bit attenuator. It permits one to set all 200 attenuators of a typical hybrid computer installation within 20 milliseconds. For maximum contact life, relay contacts are switched only when no current is flowing. The digital computer static-check routine can readily check individual relays to simplify maintenance. Particular emphasis in this report is on a digital-attenu ator system designed for a very fast repetitive computer in the Analog/Hybrid Computing Laboratory at the Uni versity of Arizona. The same design approach is readily applied to "slow" analog computers and appears to be even more advantageous there.

scholarly journals Improved Precoder Architecture for Duobinary Transceivers

2017 ◽  
Vol 5 ◽  
Author(s):  
Javier Aguirre Olcoz ◽  
C. Sánchez-Azqueta ◽  
E. Guerrero ◽  
C. Gimeno ◽  
S. Celma
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Cmos Technology ◽  
Modulation Scheme ◽  
Serial Data ◽  
Soi Cmos

Duobinary modulation is an attractive baseband modulation scheme for high-speed serial data transmission. This work presents a duobinary transceiver with a new precoder architecture that overcomes the glitch vulnerability of the conventional ones. It has been fabricated in a 0.13-μm PD-SOI CMOS technology and achieves 10 Gbps consuming 37 mW. 

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