scholarly journals The BER performance of a FSO system with polar codes under weak turbulence

2021 ◽  
Author(s):  
Nithin Mohan ◽  
Zabih Ghassemlooy ◽  
Emma Li ◽  
Mojtaba Mansour Abadi ◽  
Stanislav Zvanovec ◽  
...  
Keyword(s):  
Polar Codes ◽  
Weak Turbulence ◽  
Ber Performance

Adaptive rate polar codes for atmospheric weak turbulence channel

2019 ◽  
Vol 48 (7) ◽  
pp. 722004
Author(s):  
张 晗 Zhang Han ◽  
涂巧玲 Tu Qiaoling ◽  
曹 阳 Cao Yang ◽  
李小红 Li Xiaohong ◽  
彭小峰 Peng Xiaofeng
Keyword(s):  
Polar Codes ◽  
Weak Turbulence ◽  
Adaptive Rate

scholarly journals Priority Queue VLSI Architecture for Sequential Decoder of Polar Codes

2021 ◽  
Author(s):  
Andrey Rashich ◽  
Aleksei Krylov ◽  
Dmitrii Fadeev ◽  
Kirill Sinjutin
Keyword(s):  
Vlsi Architecture ◽  
Priority Queue ◽  
Low Complexity ◽  
Low Latency ◽  
Polar Codes ◽  
Sorting Networks ◽  
Vlsi Architectures ◽  
Simulation Results ◽  
Full Search ◽  
Ber Performance

<div>The VLSI architectures for stack or priority queue (PQ) are required in the implementation of stack or sequential decoders of polar codes. Such type of decoders provide good BER performance keeping complexity low. Extracting the best and the worst paths from PQ is the most complex operation in terms of both latency and complexity, because this operation requires full search along priority queue. In this work we propose a low latency and low complexity parallel hardware architecture for PQ, which is based on the systolic sorter and simplified sorting primitives. The simulation results show that just small BER degradation is introduced compared to ideal full sorting networks. Proposed PQ architecture is implemented in FPGA, the synthesis results are presented for all components of PQ.</div>

scholarly journals Priority Queue VLSI Architecture for Sequential Decoder of Polar Codes

2021 ◽  
Author(s):  
Andrey Rashich ◽  
Aleksei Krylov ◽  
Dmitrii Fadeev ◽  
Kirill Sinjutin
Keyword(s):  
Vlsi Architecture ◽  
Priority Queue ◽  
Low Complexity ◽  
Low Latency ◽  
Polar Codes ◽  
Sorting Networks ◽  
Vlsi Architectures ◽  
Simulation Results ◽  
Full Search ◽  
Ber Performance

<div>The VLSI architectures for stack or priority queue (PQ) are required in the implementation of stack or sequential decoders of polar codes. Such type of decoders provide good BER performance keeping complexity low. Extracting the best and the worst paths from PQ is the most complex operation in terms of both latency and complexity, because this operation requires full search along priority queue. In this work we propose a low latency and low complexity parallel hardware architecture for PQ, which is based on the systolic sorter and simplified sorting primitives. The simulation results show that just small BER degradation is introduced compared to ideal full sorting networks. Proposed PQ architecture is implemented in FPGA, the synthesis results are presented for all components of PQ.</div>

An Adaptive Fusion Successive Cancellation List Decoder for Polar Codes with Cyclic Redundancy Check

2020 ◽  
Vol E103.B (1) ◽  
pp. 43-51 ◽  
Author(s):  
Yuhuan WANG ◽  
Hang YIN ◽  
Zhanxin YANG ◽  
Yansong LV ◽  
Lu SI ◽  
...  
Keyword(s):  
Polar Codes ◽  
Cyclic Redundancy Check ◽  
Successive Cancellation ◽  
Adaptive Fusion ◽  
List Decoder

Compact specification of polar codes

2019 ◽  
pp. 40-47
Author(s):  
R. A. Morozov ◽  
P. V. Trifonov
Keyword(s):  
Storage Capacity ◽  
Low Complexity ◽  
Practical Implementation ◽  
Polar Codes ◽  
Practical Relevance ◽  
Memory Consumption ◽  
Full Size ◽  
The Family ◽  
Erasure Probability ◽  
Binary Erasure Channel

Introduction:Practical implementation of a communication system which employs a family of polar codes requires either to store a number of large specifications or to construct the codes by request. The first approach assumes extensive memory consumption, which is inappropriate for many applications, such as those for mobile devices. The second approach can be numerically unstable and hard to implement in low-end hardware. One of the solutions is specifying a family of codes by a sequence of subchannels sorted by reliability. However, this solution makes it impossible to separately optimize each code from the family.Purpose:Developing a method for compact specifications of polar codes and subcodes.Results:A method is proposed for compact specification of polar codes. It can be considered a trade-off between real-time construction and storing full-size specifications in memory. We propose to store compact specifications of polar codes which contain frozen set differences between the original pre-optimized polar codes and the polar codes constructed for a binary erasure channel with some erasure probability. Full-size specification needed for decoding can be restored from a compact one by a low-complexity hardware-friendly procedure. The proposed method can work with either polar codes or polar subcodes, allowing you to reduce the memory consumption by 15–50 times.Practical relevance:The method allows you to use families of individually optimized polar codes in devices with limited storage capacity. 

Polar Codes

2014 ◽  
Author(s):  
David Wasserman
Keyword(s):  
Polar Codes
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