High frequency performance of dual metal gate vertical tunnel field effect transistor based on work function engineering

2016 ◽  
Vol 11 (6) ◽  
pp. 319-322 ◽  
Author(s):  
Kaushal Nigam ◽  
Pravin Kondekar ◽  
Dheeraj Sharma
Author(s):  
Tianyu Yu ◽  
Liang Dai ◽  
Zhifeng Zhao ◽  
Weifeng Lyu ◽  
Mi Lin

The impact of work-function variation (WFV) on performance of an inversion-mode (IM) dual-metal gate (DMG) fin field-effect transistor (FinFET) was investigated for the first time. The statistical fluctuations induced by WFV on the threshold-voltage (VTH), transconductance (gm), and subthreshold slope (SS) were demonstrated and estimated utilizing a 3D technology computer-aided design (TCAD) simulator. We found that the performance variations of the DMG FinFET were affected by two different metals near the drain and near the source, respectively. Additionally, this effect of the two metals on the channel was not monotonic with the length of the channel of their own control. Our work fills a gap in the study of WFV for a DMG IM FinFET and provides a reference for optimizing the distribution of the two metals.


2001 ◽  
Author(s):  
Hirotada Taniuchi ◽  
Hitoshi Umezawa ◽  
Hiroaki Ishizaka ◽  
Takuya Arima ◽  
Hiroshi Kawarada

Tunnel Field Effect Transistor (TFET) is gated reverse biased P-I-N diode structured semiconductor device and can be considered as a reliable low power device. TCAD (Sentaurus 2D) simulations for various Gate metal work function (4.1-4.3 eV) shows that its ON-current (ION) arises from quantum mechanical band-to-band tunneling (B2BT) and observed that threshold Voltage (VT) for TFET decreases with increase in Gate metal work function. The thermionic emission of electrons in MOSFET limits the sub-threshold swing (SS) by 60 mV/dec whereas TFET has potential for low SS ie. SS<60 mV/dec. TCAD Simulations confirmed that that the Gate – Drain capacitance (Cgd) strongly follows the Gate capacitance (Cgg) all over the voltage range (0-0.9V) which increases the miller capacitance for TFET. It is investigated that for TFET, the injection of carriers into the channel is through B2BT which effectively couples the Gate charge to the Drain. A look up table based Verilog-A model is generated for TFET and used to simulate the static and dynamic behavior of TFET based digital circuit in Cadence spectre. Miller effect causes the peak voltage overshoots are noticed at the drain side during transient responses and can be responsible for dynamic power loss and high turn ON/OFF delay


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