scholarly journals 23 µW 8.9-effective number of bit 1.1 MS/s successive approximation register analog-to-digital converter with an energy-efficient digital-to-analog converter switching scheme

2014 ◽  
Vol 2014 (8) ◽  
pp. 420-425
Author(s):  
Lei Sun ◽  
Chi Tung Ko ◽  
Marco Ho ◽  
Wai Tung Ng ◽  
Ka Nang Leung ◽  
...  
Keyword(s):  
Successive Approximation ◽  
Energy Efficient ◽  
Analog To Digital Converter ◽  
Effective Number ◽  
Digital Converter ◽  
Switching Scheme ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Successive Approximation Register ◽  
Analog Converter

Energy-Efficient Switching Scheme with 93.41% Reduction in Capacitor Area for SAR ADC

2019 ◽  
Vol 28 (13) ◽  
pp. 1930010 ◽  
Author(s):  
Shubin Liu ◽  
Haolin Han ◽  
Ruixue Ding
Keyword(s):  
Successive Approximation ◽  
Energy Efficient ◽  
Sar Adc ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Switching Scheme ◽  
Analog To Digital ◽  
Capacitor Array ◽  
Asymmetric Capacitor ◽  
Conventional Scheme

A novel switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. Based on the asymmetric capacitor array and splitted MSB capacitor, the proposed scheme achieves 99.09% and 93.41% reductions in the average switching energy and capacitor area, respectively, over the conventional scheme. Moreover, the proposed SAR ADC obtains a moderate linearity performance with max(INL-RMS) less than 0.112 LSB, max(DNL-RMS) less than 0.160 LSB and consumes zero reset energy.

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