Programmable Logic Handbook

IEE Review ◽  
1988 ◽  
Vol 34 (2) ◽  
pp. 86
Author(s):  
A.P. Dorey
Keyword(s):  
Programmable Logic

Desain Media Pembelajaran Sistem Kontrol Elektropneumatik Berbasis Programmable Logic Controller

2018 ◽  
Vol 3 (1) ◽  
pp. 42
Author(s):  
Wachid Yahya
Keyword(s):  
Research And Development ◽  
Programmable Logic Controller ◽  
Programmable Logic

Sistem kontrol elektropneumatik telah banyak digunakan dalam menunjang pekerjaan di dunia industri,perkembangan teknologi ini harus segera direspons oleh dosen pada perguruan tinggi vokasi yang memiliki peran sebagai pencetak calon tenaga ahli siap kerjauntuk mengembangkan media pembelajaran. Penelitian ini bertujuan untuk: (1) menguji kelayakan desain media pembelajaran sistem kontrol elektropneumatik berbasis <em>programmable logic controller</em>, (2) mendeskripsikan respons mahasiswa dalam menggunakan media pembelajaran sistem kontrol elektropneumatik berbasis <em>programmable logic controller</em> dalam kegiatan pembelajaran. Metode yang digunakan pada penelitian ini yaitu menggunakan metode penelitian dan pengembangan <em>Research and Development</em> (R&amp;D) dengan melalui beberapa tahap, yaitu tahap analisis potensi dan masalah, pengumpulan data, desain produk, validasi desain, revisi desain, uji coba produk, revisi produk, dan uji coba pemakaian. Pengumpulan data dilakukan dengan menggunakan lembar validasi ahli yang diberikan oleh 3 orang ahli dan angket respons yang diperoleh dari mahasiswa. Kesimpulan yang diperoleh dari penelitian ini yaitu: (1) desain pembelajaran sistem kontrol elektropneumatik berbasis <em>programmable logic controller</em> mendapatkan nilai validasi yang diberikan oleh para ahli dengan rata-rata nilai 3,51 sehingga menunjukkan bahwa media pembelajaran dalam kategori baik dan layak untuk digunakan dalam proses pembelajaran, (2) respons mahasiswa dalam menggunakan media pembelajaran sistem kontrol elektropneumatik berbasis <em>programmable logic controller </em>dalam kegiatan pembelajaran diperoleh nilai persentase 84,34%mahasiswa memberikan respons menarik, dengan demikian hasil respons mahasiswa termasuk dalam kategori baik.

scholarly journals Petri Net-Based Semi-Compiled Code Generation for Programmable Logic Controllers

2021 ◽  
Vol 11 (15) ◽  
pp. 7161
Author(s):  
Igor Azkarate ◽  
Mikel Ayani ◽  
Juan Carlos Mugarza ◽  
Luka Eciolaza
Keyword(s):  
Code Generation ◽  
Resource Sharing ◽  
Discrete Event ◽  
Transition Function ◽  
Discrete Event Dynamic Systems ◽  
Programmable Logic ◽  
External Software ◽  
Implementation Methodology ◽  
Event Dynamic ◽  
Step Transition

Industrial discrete event dynamic systems (DEDSs) are commonly modeled by means of Petri nets (PNs). PNs have the capability to model behaviors such as concurrency, synchronization, and resource sharing, compared to a step transition function chart or GRAphe Fonctionnel de Commande Etape Transition (GRAFCET) which is a particular case of a PN. However, there is not an effective systematic way to implement a PN in a programmable logic controller (PLC), and so the implementation of such a controller outside a PLC in some external software that will communicate with the PLC is very common. There have been some attempts to implement PNs within a PLC, but they are dependent on how the logic of places and transitions is programmed for each application. This work proposes a novel application-independent and platform-independent PN implementation methodology. This methodology is a systematic way to implement a PN controller within industrial PLCs. A great portion of the code will be validated automatically prior to PLC implementation. Net structure and marking evolution will be checked on the basis of PN model structural analysis, and only net interpretation will be manually coded and error-prone. Thus, this methodology represents a systematic and semi-compiled PN implementation method. A use case supported by a digital twin (DT) is shown where the automated solution required by a manufacturing system is carried out and executed in two different devices for portability testing, and the scan cycle periods are compared for both approaches.

scholarly journals Evaluating Latency in Multiprocessing Embedded Systems for the Smart Grid

Energies ◽  
2021 ◽  
Vol 14 (11) ◽  
pp. 3322
Author(s):  
Sara Alonso ◽  
Jesús Lázaro ◽  
Jaime Jiménez ◽  
Unai Bidarte ◽  
Leire Muguira
Keyword(s):  
Operating System ◽  
Smart Grid ◽  
Real Time ◽  
Processing System ◽  
The Other ◽  
Programmable Logic ◽  
Detailed Characterization ◽  
Timing Constraint ◽  
Time Part

Smart grid endpoints need to use two environments within a processing system (PS), one with a Linux-type operating system (OS) using the Arm Cortex-A53 cores for management tasks, and the other with a standalone execution or a real-time OS using the Arm Cortex-R5 cores. The Xen hypervisor and the OpenAMP framework allow this, but they may introduce a delay in the system, and some messages in the smart grid need a latency lower than 3 ms. In this paper, the Linux thread latencies are characterized by the Cyclictest tool. It is shown that when Xen hypervisor is used, this scenario is not suitable for the smart grid as it does not meet the 3 ms timing constraint. Then, standalone execution as the real-time part is evaluated, measuring the delay to handle an interrupt created in programmable logic (PL). The standalone application was run in A53 and R5 cores, with Xen hypervisor and OpenAMP framework. These scenarios all met the 3 ms constraint. The main contribution of the present work is the detailed characterization of each real-time execution, in order to facilitate selecting the most suitable one for each application.

Sign in / Sign up

Export Citation Format

Share Document