Fault effects in asynchronous sequential logic circuits

M.-D. Shieh; C.-L. Wey; P.D. Fisher

doi:10.1049/ip-e.1993.0046

Fault effects in asynchronous sequential logic circuits

IEE Proceedings E (Computers and Digital Techniques) ◽

10.1049/ip-e.1993.0046 ◽

1993 ◽

Vol 140 (6) ◽

pp. 327-332

Author(s):

M.-D. Shieh ◽

C.-L. Wey ◽

P.D. Fisher

Keyword(s):

Logic Circuits ◽

Sequential Logic

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Synthesis of synchronous sequential logic circuits from partial input/output sequences

Evolvable Systems: From Biology to Hardware - Lecture Notes in Computer Science ◽

10.1007/bfb0057611 ◽

1998 ◽

pp. 98-105 ◽

Cited By ~ 8

Author(s):

Chaiyasit Manovit ◽

Chatchawit Aporntewan ◽

Prabhas Chongstitvatana

Keyword(s):

Logic Circuits ◽

Input Output ◽

Sequential Logic

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Scan Design for Sequential Logic Circuits

Logic Testing and Design for Testability ◽

10.7551/mitpress/4317.003.0012 ◽

1985 ◽

Keyword(s):

Logic Circuits ◽

Scan Design ◽

Sequential Logic

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The design of sequential logic circuits

Electronic Logic Circuits ◽

10.4324/9780080928494-10 ◽

2013 ◽

pp. 84-103

Keyword(s):

Logic Circuits ◽

Sequential Logic

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A scan design for asynchronous sequential logic circuits using SR-latches

Proceedings of 36th Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.1993.343339 ◽

2002 ◽

Cited By ~ 5

Author(s):

Ming-Der Shieh ◽

Chin-Long Wey ◽

P.D. Fisher

Keyword(s):

Logic Circuits ◽

Scan Design ◽

Sequential Logic

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Power-Gating Adiabatic Flip-Flops and Sequential Logic Circuits

2007 International Conference on Communications, Circuits and Systems ◽

10.1109/icccas.2007.4348219 ◽

2007 ◽

Cited By ~ 4

Author(s):

Jianping Hu ◽

Dong Zhou ◽

Ling Wang

Keyword(s):

Logic Circuits ◽

Power Gating ◽

Sequential Logic

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Robust Flip-Flop against Soft Errors for Combinational and Sequential Logic Circuits

10.7567/ssdm.2008.d-2-5 ◽

2008 ◽

Cited By ~ 1

Author(s):

T. Uemura ◽

Y. Tosaka ◽

H. Matsuyama ◽

K. Takahisa ◽

K. Hatanaka

Keyword(s):

Soft Errors ◽

Logic Circuits ◽

Flip Flop ◽

Sequential Logic

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Design and Simulation of Novel D Flip-Flop Based Sequential Logic Circuits in QCA

Advanced Science Letters ◽

10.1166/asl.2017.10397 ◽

2017 ◽

Vol 23 (10) ◽

pp. 10102-10106 ◽

Cited By ~ 1

Author(s):

J. S Lee ◽

J. C Jeon

Keyword(s):

Logic Circuits ◽

Flip Flop ◽

Sequential Logic

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Waiting false path analysis of sequential logic circuits for performance optimization

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) ◽

10.1109/iccad.1998.742902 ◽

2002 ◽

Cited By ~ 1

Author(s):

K. Nakamura ◽

K. Takagi ◽

S. Kimura ◽

K. Watanabe

Keyword(s):

Path Analysis ◽

Performance Optimization ◽

Logic Circuits ◽

Sequential Logic ◽

False Path

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Design and analysis of adiabatic complex sequential logic circuits in sub-threshold regime for ultra-low power application

2016 International Conference on Communication and Signal Processing (ICCSP) ◽

10.1109/iccsp.2016.7754506 ◽

2016 ◽

Cited By ~ 1

Author(s):

Manash Chanda ◽

Diptansu Sinha ◽

Jeet Basak ◽

Tanushree Ganguli ◽

Chandan K. Sarkar

Keyword(s):

Low Power ◽

Logic Circuits ◽

Ultra Low Power ◽

Sequential Logic ◽

Power Application ◽

Threshold Regime

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Power estimation methods for sequential logic circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.406998 ◽

1995 ◽

Vol 3 (3) ◽

pp. 404-416 ◽

Cited By ~ 69

Author(s):

Chi-Ying Tsui ◽

J. Monteiro ◽

Massoud Pedram ◽

Srinivas Devadas ◽

A.M. Despain ◽

...

Keyword(s):

Power Estimation ◽

Logic Circuits ◽

Estimation Methods ◽

Sequential Logic

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