High-throughput, reduced hardware systolic solution to prime factor discrete fourier transform algorithm

1990 ◽  
Vol 137 (3) ◽  
pp. 191 ◽  
Author(s):  
K.J. Jones
2006 ◽  
Vol 176 (1) ◽  
pp. 1-26 ◽  
Author(s):  
T TRUONG ◽  
P CHEN ◽  
L WANG ◽  
Y CHANG ◽  
I REED

Author(s):  
Gourav Jain ◽  
Shaik Rafi Ahamed

In this paper, the authors propose a new systolic array for radix-2, N-point discrete Fourier Transform (DFT) computation based on CORDIC (CO-ordinate Rotation Digital Computer). Complex multiplication can be done by this in a rather simple and elegant way. A CORDIC based multiplier less DFT architecture is designed in order to improve the performance of the system. It is able to provide two transforms per each clock cycle. The proposed design is well suited for high speed DSP-applications.


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