VLSI design for diminished-1 multiplication of integers modulo a Fermat number

M. Benaissa; A. Pajayakrit; S.S. Dlay; A.G.J. Holt

doi:10.1049/ip-e.1988.0019

VLSI design for diminished-1 multiplication of integers modulo a Fermat number

IEE Proceedings E Computers and Digital Techniques ◽

10.1049/ip-e.1988.0019 ◽

1988 ◽

Vol 135 (3) ◽

pp. 161 ◽

Cited By ~ 3

Author(s):

M. Benaissa ◽

A. Pajayakrit ◽

S.S. Dlay ◽

A.G.J. Holt

Keyword(s):

Vlsi Design ◽

Fermat Number

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The VLSI design of a single chip for the multiplication of integers modulo a Fermat number

IEEE Transactions on Acoustics Speech and Signal Processing ◽

10.1109/tassp.1985.1164761 ◽

1985 ◽

Vol 33 (6) ◽

pp. 1599-1602 ◽

Cited By ~ 3

Author(s):

Jaw Chang ◽

T. Truong ◽

H. Shao ◽

I. Reed ◽

In-Shek Hsu

Keyword(s):

Vlsi Design ◽

Single Chip ◽

Fermat Number

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The VLSI design of a single chip for the multiplication of integers modulo a fermat number

10.1109/icassp.1985.1168230 ◽

2005 ◽

Cited By ~ 4

Author(s):

J. Chang ◽

T. Truong ◽

H. Shao ◽

I. Reed ◽

I. Hsu

Keyword(s):

Vlsi Design ◽

Single Chip ◽

Fermat Number

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CMOS VLSI design of a high-speed Fermat number transform based convolver/correlator using three-input adders

IEE Proceedings G Circuits Devices and Systems ◽

10.1049/ip-g-2.1991.0035 ◽

1991 ◽

Vol 138 (2) ◽

pp. 182 ◽

Cited By ~ 4

Author(s):

M. Benaissa ◽

S.S. Dlay ◽

A.G.J. Holt

Keyword(s):

High Speed ◽

Vlsi Design ◽

Fermat Number ◽

Cmos Vlsi

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Advanced Model Order Reduction Techniques in VLSI Design

10.1017/cbo9780511541117 ◽

2007 ◽

Cited By ~ 77

Author(s):

Sheldon Tan ◽

Lei He

Keyword(s):

Model Order Reduction ◽

Vlsi Design ◽

Order Reduction ◽

Model Order ◽

Reduction Techniques ◽

Advanced Model

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Theoretical Foundations of VLSI Design

10.1017/cbo9780511569838 ◽

1990 ◽

Cited By ~ 5

Keyword(s):

Vlsi Design ◽

Theoretical Foundations

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Relationship between the Fermat number transform and the Walsh-Hadamard transform

IEE Proceedings G Circuits Devices and Systems ◽

10.1049/ip-g-2.1989.0035 ◽

1989 ◽

Vol 136 (4) ◽

pp. 191 ◽

Cited By ~ 2

Author(s):

S. Boussakta ◽

A.G.J. Holt

Keyword(s):

Hadamard Transform ◽

Fermat Number ◽

Walsh Hadamard Transform

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Calculation of the discrete hartley transform via the fermat number transform using a VLSI chip

IEE Proceedings G (Electronic Circuits and Systems) ◽

10.1049/ip-g-1.1988.0014 ◽

1988 ◽

Vol 135 (3) ◽

pp. 101 ◽

Cited By ~ 2

Author(s):

S. Boussakta ◽

A.G.J. Holt

Keyword(s):

Discrete Hartley Transform ◽

Hartley Transform ◽

Vlsi Chip ◽

Fermat Number

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Switchbox routing with rerouting capabilities in VLSI design

IEE Proceedings G Circuits Devices and Systems ◽

10.1049/ip-g-2.1990.0032 ◽

1990 ◽

Vol 137 (3) ◽

pp. 210 ◽

Cited By ~ 1

Author(s):

F. Curatelli

Keyword(s):

Vlsi Design

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VLSI Design of Karatsuba Integer Multipliers and Its Evaluation

IEEJ Transactions on Electronics Information and Systems ◽

10.1541/ieejeiss.128.220 ◽

2008 ◽

Vol 128 (2) ◽

pp. 220-230 ◽

Cited By ~ 1

Author(s):

Syunji Yazaki ◽

Kôki Abe

Keyword(s):

Vlsi Design

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Photomask Data Prioritization Based on VLSI Design Intent and Its Utilization for Mask Manufacturing

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e93.a.2424 ◽

2010 ◽

Vol E93-A (12) ◽

pp. 2424-2432

Author(s):

Kokoro KATO ◽

Masakazu ENDO ◽

Tadao INOUE ◽

Shigetoshi NAKATAKE ◽

Masaki YAMABE ◽

...

Keyword(s):

Vlsi Design ◽

Design Intent

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