Realisation of multiple-valued functions using the capacitive threshold logic gate

2004 ◽  
Vol 151 (6) ◽  
pp. 435 ◽  
Author(s):  
A. Schmid ◽  
Y. Leblebici
Keyword(s):  
Logic Gate ◽  
Threshold Logic

Low-cost BSA technique for threshold-logic gate based multiplier implementations

1997 ◽  
Vol 33 (12) ◽  
pp. 1028
Author(s):  
J.M. Quintana ◽  
M.J. Avedillo ◽  
A. Rueda
Keyword(s):  
Low Cost ◽  
Logic Gate ◽  
Threshold Logic

A threshold logic gate based on clocked coupled inverters

1998 ◽  
Vol 84 (4) ◽  
pp. 371-382 ◽  
Author(s):  
J. FERNANDEZ RAMOS J. A. HIDALGO LO
Keyword(s):  
Logic Gate ◽  
Threshold Logic

A Balanced Capacitive Threshold-Logic Gate

2004 ◽  
Vol 40 (1) ◽  
pp. 61-69 ◽  
Author(s):  
Javier López-García ◽  
José Fernández-Ramos ◽  
Alfonso Gago-Bohórquez
Keyword(s):  
Logic Gate ◽  
Threshold Logic

Novel universal threshold logic gate based on RTD and its application

2011 ◽  
Vol 42 (6) ◽  
pp. 851-854 ◽  
Author(s):  
Yi Wei ◽  
Jizhong Shen
Keyword(s):  
Logic Gate ◽  
Threshold Logic

An Adaptive Threshold Logic Gate Using Capacitive Analog Weights

1968 ◽  
Vol C-17 (1) ◽  
pp. 78-81 ◽  
Author(s):  
John R. Smith ◽  
Cyrus O. Harbourt
Keyword(s):  
Logic Gate ◽  
Adaptive Threshold ◽  
Threshold Logic

scholarly journals An Accumulator using Electron Tunneling Through Tunnel Junction

2021 ◽  
pp. 163-183
Author(s):  
Dr. Anup Kumar Biswas
Keyword(s):  
High Speed ◽  
Electron Tunneling ◽  
Low Cost ◽  
Logic Gate ◽  
Logic Gates ◽  
Threshold Logic ◽  
High Concentration ◽  
Flip Flop ◽  
Linear Threshold ◽  
Parameter Values

Instead of an existing logical Technology, by using an emerging technology we will be able to make an electronic circuit with high speed, low cost, high concentration density, light in weight, reduced gate numbers and low power consumption. This technology is based on the linear threshold logic condition and electron-tunneling event. At the time of implementing a circuit, a multi-inputs but one-output based logic-node will be brought in our consideration. In this work, we have designed a 1-bit accumulator and then implemented it. To develop an accumulator, some small components like 2-input AND, 3-input AND, 3-input OR, 8-input OR, 9-input OR gate and above all a JK Flip-flop (for 1-bit) are to be collected and connected them in logical order to obtain the proper circuit. After verifying all their characteristics with the results obtained from the simulator, we have built a 1-bit accumulator. All the small components are provided in due places. They are analyzed, detected their threshold logic equations, shown their threshold logic gates (TLGs), tabulated their truth tables, drawn their input-output waveforms, given their respective circuits with exact parameter values. In the accumulator, there are nine control variables S1 through S9 in view of performing the operations (i) Addition, (ii) clear, (iii) complement, (iv) AND, (v) OR, (vi) XOR, (vii) Right-shift, (viii) Left-shift and (ix) increment with positive triggering clock pulses. Whether our present work’s circuits are faster or slower with respect to the similar circuits of CMOS based- and Single electron transistor (SET) based circuits are compared and observed that our TLG based circuits are faster than the CMOS and SET based circuits. The power consumed for tunneling event for a circuit is measured and sensed that it would remain in the range of 10meV to 250meV which is low. All the circuits we have presented in this work are of ‘generic multiple input threshold logic gate’ which is elaborately discussed.

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