Logic simulation methods for longest path delay estimation

2002 ◽  
Vol 149 (2) ◽  
pp. 53 ◽  
Author(s):  
D.M. Maksimović ◽  
V.B. Litovski
Keyword(s):  
Delay Estimation ◽  
Simulation Methods ◽  
Path Delay ◽  
Logic Simulation ◽  
Longest Path

scholarly journals Spatially Correlated Sparse MIMO Channel Path Delay Estimation in Scattering Environments Based on Signal Subspace Tracking

Sensors ◽  
2018 ◽  
Vol 18 (5) ◽  
pp. 1451 ◽  
Author(s):  
Ali Mohydeen ◽  
Pascal Chargé ◽  
Yide Wang ◽  
Oussama Bazzi ◽  
Yuehua Ding
Keyword(s):  
Delay Estimation ◽  
Mimo Channel ◽  
Signal Subspace ◽  
Subspace Tracking ◽  
Path Delay ◽  
Spatially Correlated

scholarly journals A Timing-Driven Partitioning System for Multiple FPGAs

VLSI Design ◽  
1996 ◽  
Vol 4 (4) ◽  
pp. 309-328
Author(s):  
Kalapi Roy ◽  
Carl Sechen
Keyword(s):  
Simulated Annealing ◽  
Performance Optimization ◽  
Clustering Algorithm ◽  
Linear Time ◽  
Critical Path ◽  
Path Delay ◽  
Timing Model ◽  
Longest Path ◽  
Partitioning Algorithm ◽  
Circuit Components

Field-programmable systems with multiple FPGAs on a PCB or an MCM are being used by system designers when a single FPGA is not sufficient. We address the problem of partitioning a large technology mapped FPGA circuit onto multiple FPGA devices of a specific target technology. The physical characteristics of the multiple FPGA system (MFS) pose additional constraints to the circuit partitioning algorithms: the capacity of each FPGA, the timing constraints, the number of I/Os per FPGA, and the pre-designed interconnection patterns of each FPGA and the package. Existing partitioning techniques which minimize just the cut sizes of partitions fail to satisfy the above challenges. We therefore present a timing driven N-way partitioning algorithm based on simulated annealing for technology-mapped FPGA circuits. The signal path delays are estimated during partitioning using a timing model specific to a multiple FPGA architecture. The model combines all possible delay factors in a system with multiple FPGA chips of a target technology. Furthermore, we have incorporated a new dynamic net-weighting scheme to minimize the number of pin-outs for each chip. Finally, we have developed a graph-based global router for pin assignment which can handle the pre-routed connections of our MFS structure. In order to reduce the time spent in the simulated annealing phase of the partitioner, clusters of circuit components are identified by a new linear-time bottom-up clustering algorithm. The annealing-based N-way partitioner executes four times faster using the clusters as opposed to a flat netlist with improved partitioning results. For several industrial circuits, our approach outperforms the recursive min-cut bi-partitioning algorithm by 35% in terms of nets cut. Our approach also outperforms an industrial FPGA partitioner by 73% on average in terms of unroutable nets. Using the performance optimization capabilities in our approach we have successfully partitioned the MCNC benchmarks satisfying the critical path constraints and achieving a significant reduction in the longest path delay. An average reduction of 17% in the longest path delay was achieved at the cost of 5% in total wire length.

Acoustic echo path delay estimation by means of a BOC-BPSK correlation method

2015 ◽  
Author(s):  
F. Beaubois ◽  
I. Selmi ◽  
J. B. Choquel ◽  
J. C. Noyer ◽  
S. Reboul
Keyword(s):  
Correlation Method ◽  
Delay Estimation ◽  
Path Delay ◽  
Acoustic Echo
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