2 GHz controllable power amplifier in standard CMOS process for short-range wireless applications

2002 ◽  
Vol 149 (5) ◽  
pp. 363-368 ◽  
Author(s):  
M.M. Hella ◽  
M. Ismail
Keyword(s):  
Power Amplifier ◽  
Short Range ◽  
Cmos Process ◽  
Wireless Applications ◽  
Standard Cmos Process

Design of high-Q varactors for low-power wireless applications using a standard CMOS process

2000 ◽  
Vol 35 (3) ◽  
pp. 337-345 ◽  
Author(s):  
A.-S. Porret ◽  
T. Melly ◽  
C.C. Enz ◽  
E.A. Vittoz
Keyword(s):  
Low Power ◽  
Cmos Process ◽  
Wireless Applications ◽  
High Q ◽  
Standard Cmos Process

Fabrication of Monolithic Integrated Bimaterial Resonant Uncooled IR Sensor

2013 ◽  
Vol 543 ◽  
pp. 176-179 ◽  
Author(s):  
D.Q. Zhao ◽  
Xia Zhang ◽  
P. Liu ◽  
F. Yang ◽  
C. Lin ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Hole Mobility ◽  
Micro Electro Mechanical System ◽  
Cmos Process ◽  
Standard Cmos Process ◽  
Ir Sensor ◽  
Cantilever Structure ◽  
Cmos Mems ◽  
On Chip ◽  
Micro Cantilever

In this work we studied the fabrication of a monolithic bimaterial micro-cantilever resonant IR sensor with on-chip drive circuits. The effects of high temperature process and stress induced performance degradation were investigated. The post-CMOS MEMS (micro electro mechanical system) fabrication process of this IR sensor is the focus of this paper, starting from theoretical analysis and simulation, and then moving to experimental verification. The capacitive cantilever structure was fabricated by surface micromachining method, and drive circuits were prepared by standard CMOS process. While the stress introduced by MEMS films, such as the tensile silicon nitride which works as a contact etch stopper layer for MOSFETs and releasing stop layer for the MEMS structure, increases the electron mobility of NMOS, PMOS hole mobility decreases. Moreover, the NMOS threshold voltage (Vth) shifts, and transconductance (Gm) degrades. An additional step of selective removing silicon nitride capping layer and polysilicon layer upon IC area were inserted into the standard CMOS process to lower the stress in MOSFET channel regions. Selective removing silicon nitride and polysilicon before annealing can void 77% Vth shift and 86% Gm loss.

Sign in / Sign up

Export Citation Format

Share Document