Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse

A. Milidonis; V. Porpodas; N. Alachiotis; A.P. Kakarountas; H. Michail; G. Panagiotakopoulos; C.E. Goutis

doi:10.1049/iet-cdt:20070145

Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse

IET Computers & Digital Techniques ◽

10.1049/iet-cdt:20070145 ◽

2009 ◽

Vol 3 (1) ◽

pp. 109 ◽

Cited By ~ 1

Author(s):

A. Milidonis ◽

V. Porpodas ◽

N. Alachiotis ◽

A.P. Kakarountas ◽

H. Michail ◽

...

Keyword(s):

Low Power ◽

Scratch Pad Memory ◽

Run Time ◽

Embedded Applications ◽

Power Architecture

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Implementation of Stack Data Placement and Run Time Management Using a Scratch-Pad Memory for Energy Consumption Reduction of Embedded Applications

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e94.a.2597 ◽

2011 ◽

Vol E94-A (12) ◽

pp. 2597-2608 ◽

Cited By ~ 1

Author(s):

Lovic GAUTHIER ◽

Tohru ISHIHARA

Keyword(s):

Energy Consumption ◽

Time Management ◽

Data Placement ◽

Energy Consumption Reduction ◽

Scratch Pad Memory ◽

Consumption Reduction ◽

Run Time ◽

Embedded Applications

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Voltage-Gate-Assisted Spin-Orbit-Torque Magnetic Random-Access Memory for High-Density and Low-Power Embedded Applications

Physical Review Applied ◽

10.1103/physrevapplied.15.064015 ◽

2021 ◽

Vol 15 (6) ◽

Author(s):

Y.C. Wu ◽

K. Garello ◽

W. Kim ◽

M. Gupta ◽

M. Perumkunnil ◽

...

Keyword(s):

Low Power ◽

Random Access ◽

Random Access Memory ◽

High Density ◽

Spin Orbit ◽

Access Memory ◽

Magnetic Random Access Memory ◽

Embedded Applications ◽

Voltage Gate

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A low power architecture for wireless multimedia systems: lessons learned from building a power hog

Proceedings of 1996 International Symposium on Low Power Electronics and Design ◽

10.1109/lpe.1996.542725 ◽

2002 ◽

Cited By ~ 12

Author(s):

W. Mangione-Smith ◽

P.S. Ghang ◽

S. Nazareth ◽

P. Lettieri ◽

W. Boring ◽

...

Keyword(s):

Low Power ◽

Lessons Learned ◽

Multimedia Systems ◽

Wireless Multimedia ◽

Power Architecture

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A Low-Power Single-Weight-Combiner 802.11abg SoC in 0.13 µm CMOS for Embedded Applications Utilizing An Area and Power Efficient Cartesian Phase Shifter and Mixer Circuit

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2008.920338 ◽

2008 ◽

Vol 43 (5) ◽

pp. 1101-1118 ◽

Cited By ~ 19

Author(s):

A. Afsahi ◽

J.J. Rael ◽

A. Behzad ◽

Hung-Ming Chien ◽

M. Pan ◽

...

Keyword(s):

Low Power ◽

Phase Shifter ◽

Power Efficient ◽

Embedded Applications

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A Low Power Architecture for HASM Motion Tracking

The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology ◽

10.1023/b:vlsi.0000017006.75431.c7 ◽

2004 ◽

Vol 37 (1) ◽

pp. 111-127 ◽

Cited By ~ 1

Author(s):

Wael Badawy ◽

Magdy Bayoumi

Keyword(s):

Low Power ◽

Motion Tracking ◽

Power Architecture

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A Compact & Low Power Architecture of XXTEA192 Lightweight block cipher

2021 6th International Conference on Communication and Electronics Systems (ICCES) ◽

10.1109/icces51350.2021.9489097 ◽

2021 ◽

Author(s):

Chaitanya Kella ◽

Zeesha Mishra ◽

Bibhudendra Acharya

Keyword(s):

Low Power ◽

Block Cipher ◽

Lightweight Block Cipher ◽

Power Architecture

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High-performance, low-power architecture for scalable radix 2 montgomery modular multiplication algorithm

Canadian Journal of Electrical and Computer Engineering ◽

10.1109/cjece.2009.5599422 ◽

2009 ◽

Vol 34 (4) ◽

pp. 152-157 ◽

Cited By ~ 9

Author(s):

Atef Ibrahim ◽

Fayez Gebali ◽

Hamed El-Simary ◽

Amin Nassar

Keyword(s):

Low Power ◽

High Performance ◽

Modular Multiplication ◽

Multiplication Algorithm ◽

Montgomery Modular Multiplication ◽

Power Architecture

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A Low-Power Architecture for the Design of a One-Dimensional Median Filter

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2014.2368974 ◽

2015 ◽

Vol 62 (3) ◽

pp. 266-270 ◽

Cited By ~ 8

Author(s):

Ren-Der Chen ◽

Pei-Yin Chen ◽

Chun-Hsien Yeh

Keyword(s):

Low Power ◽

Median Filter ◽

One Dimensional ◽

Power Architecture

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Shadow Stack Scratch-Pad-Memory for Low Power SoC

2008 Fifth IEEE International Symposium on Embedded Computing ◽

10.1109/sec.2008.74 ◽

2008 ◽

Cited By ~ 4

Author(s):

Ling Ming ◽

Shi Xianqiang ◽

Zhang Yu

Keyword(s):

Low Power ◽

Scratch Pad Memory

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A high-speed/low-power architecture for 1D discrete biorthogonal wavelet transform

2003 46th Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.2003.1562569 ◽

2006 ◽

Author(s):

I.S. Uzun ◽

A. Amira ◽

A. Bouridane

Keyword(s):

Wavelet Transform ◽

Low Power ◽

High Speed ◽

Biorthogonal Wavelet ◽

Biorthogonal Wavelet Transform ◽

Power Architecture

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