Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism

2007 ◽  
Vol 1 (3) ◽  
pp. 197 ◽  
Author(s):  
A.M. Amory ◽  
K. Goossens ◽  
E.J. Marinissen ◽  
M. Lubaszewski ◽  
F. Moraes
Keyword(s):  
Network On Chip ◽  
Test Access Mechanism ◽  
Bus Network ◽  
On Chip

Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip

2014 ◽  
Vol 35 (2) ◽  
pp. 341-346
Author(s):  
Xiao-fu Zheng ◽  
Hua-xi Gu ◽  
Yin-tang Yang ◽  
Zhong-fan Huang
Keyword(s):  
Network On Chip ◽  
Low Latency ◽  
Router Architecture ◽  
On Chip
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