Area‐ and power‐efficient iterative single/double‐precision merged floating‐point multiplier on FPGA
2017 ◽
Vol 11
(4)
◽
pp. 149-158
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2019 ◽
Vol 8
(4)
◽
pp. 8533-8538
Keyword(s):
2016 ◽
Vol 23
(7)
◽
pp. 1669-1681
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2019 ◽
Vol 8
(2S11)
◽
pp. 2990-2993
Keyword(s):
2021 ◽
Keyword(s):