Power bumps and through‐silicon‐vias placement with optimised power mesh structure for power delivery network in three‐dimensional‐integrated circuits

2013 ◽  
Vol 7 (1) ◽  
pp. 11-20 ◽  
Author(s):  
Cheoljon Jang ◽  
Jaehwan Kim ◽  
Byunggyu Ahn ◽  
Jongwha Chong
Keyword(s):  
Integrated Circuits ◽  
Three Dimensional ◽  
Power Delivery ◽  
Through Silicon Vias ◽  
Mesh Structure ◽  
Power Delivery Network ◽  
Silicon Vias ◽  
Delivery Network

Development of Backside Buried Metal Layer Technology for 3D-ICs

2019 ◽  
Vol 2019 (1) ◽  
pp. 000268-000273
Author(s):  
Naoya Watanabe ◽  
Yuuki Araga ◽  
Haruo Shimamoto ◽  
Katsuya Kikuchi ◽  
Makoto Nagata
Keyword(s):  
Integrated Circuits ◽  
Metal Layer ◽  
Three Dimensional ◽  
Chip Thickness ◽  
Power Delivery ◽  
Silicon Structure ◽  
Metal Insulator ◽  
3D Ics ◽  
Power Delivery Network ◽  
Global Power

Abstract In this study, we developed backside buried metal (BBM) layer technology for three-dimensional integrated circuits (3D-ICs). In this technology, a BBM layer for global power routing is introduced in the large vacant area on the backside of each chip and is parallelly connected with the frontside routing of the chip. The resistances of the power supply (VDD) and ground (VSS) lines consequently decrease. In addition, the BBM structure acts as a decoupling capacitor because it is buried in the Si substrate and has metal–insulator–silicon structure. Therefore, the impedance of power delivery network can be reduced by introducing the BBM layer. The fabrication process of the BBM layer for 3D-ICs was simple and compatible with the via-last through-silicon via (TSV) process. With this process, it was possible to fabricate the BBM layer consisting of electroplated Cu (thickness: approximately 10 μm) buried in the backside of the CMOS chip (thickness: 43 μm), which was connected with the frontside routing of the chip using 9 μm-diameter TSVs.

scholarly journals Optimization of Power Bumps and TSVs with Optimized Power Mesh Structure for Power Delivery Network in 3D-ICs

2012 ◽  
Vol 16 (2) ◽  
pp. 102-108
Author(s):  
Byung-Gyu Ahn ◽  
Jae-Hwan Kim ◽  
Cheol-Jon Jang ◽  
Jong-Wha Chong
Keyword(s):  
Power Delivery ◽  
Mesh Structure ◽  
3D Ics ◽  
Power Delivery Network ◽  
Delivery Network

Modelling of crosstalk in differential through silicon vias for three‐dimensional integrated circuits

2019 ◽  
Vol 13 (10) ◽  
pp. 1529-1535
Author(s):  
Jin‐Wei Pan ◽  
Kai Fu ◽  
Qi Liu ◽  
Wen‐Sheng Zhao ◽  
Linxi Dong ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Three Dimensional ◽  
Through Silicon Vias ◽  
Silicon Vias

Copper Anisotropy Effects in Three-Dimensional Integrated Circuits Using Through-Silicon Vias

2012 ◽  
Vol 12 (2) ◽  
pp. 225-232 ◽  
Author(s):  
Aditya P. Karmarkar ◽  
Xiaopeng Xu ◽  
Kong-Boon Yeap ◽  
Ehrenfried Zschech
Keyword(s):  
Integrated Circuits ◽  
Three Dimensional ◽  
Through Silicon Vias ◽  
Silicon Vias
Sign in / Sign up

Export Citation Format

Share Document