Analogue high-level synthesis for mixed-signal IC realisation using an Analogue Design Synthesis Assistant (ADSA)

2000 ◽  
Author(s):  
R.E. Massara
Keyword(s):  
High Level Synthesis ◽  
Design Synthesis ◽  
Mixed Signal ◽  
High Level ◽  
Mixed Signal Ic

scholarly journals High-level Synthesis Integrated Verification

2015 ◽  
Vol 5 (5) ◽  
pp. 864-870
Author(s):  
M. Dossis
Keyword(s):  
Great Proportion ◽  
Experimental Work ◽  
Integrated Approach ◽  
High Level Synthesis ◽  
Ic Design ◽  
Program Code ◽  
Design Synthesis ◽  
Design Project ◽  
Synthesis Tool ◽  
High Level

It is widely known in the engineering community that more than 60% of the IC design project time is spent on verification. For the very complex contemporary chips, this may prove prohibitive for the IC to arrive at the correct time in the market and therefore, valuable sales share may be lost by the developing industry. This problem is deteriorated by the fact that most of conventional verification flows are highly repetitive and a great proportion of the project time is spent on last-moment simulations. In this paper we present an integrated approach to rapid, high-level verification, exploiting the advantages of a formal High-level Synthesis tool, developed by the author.  Verification in this work is supported at 3 levels: high-level program code, RTL simulation and rapid, generated C testbench execution. This paper is supported by strong experimental work with 3-4 popular design synthesis and verification that proves the principles of our methodology.

Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

2009 ◽  
Vol E92-A (12) ◽  
pp. 3169-3179 ◽  
Author(s):  
Akira OHCHI ◽  
Nozomu TOGAWA ◽  
Masao YANAGISAWA ◽  
Tatsuo OHTSUKI
Keyword(s):  
High Level Synthesis ◽  
High Level

Exact and Practical Modulo Scheduling for High-Level Synthesis

2019 ◽  
Vol 12 (2) ◽  
pp. 1-26 ◽  
Author(s):  
Julian Oppermann ◽  
Melanie Reuter-Oppermann ◽  
Lukas Sommer ◽  
Andreas Koch ◽  
Oliver Sinnen
Keyword(s):  
High Level Synthesis ◽  
Modulo Scheduling ◽  
High Level
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