scholarly journals Mixed-signal custom IC control processors incorporating design for test/self-test

1997 ◽  
Author(s):  
I.A. Grout
Keyword(s):  
Design For Test ◽  
Mixed Signal ◽  
Self Test

On-chip ramp generators for mixed-signal BIST and ADC self-test

2003 ◽  
Vol 38 (2) ◽  
pp. 263-273 ◽  
Author(s):  
B. Provost ◽  
E. Sanchez-Sinencio
Keyword(s):  
Mixed Signal ◽  
Self Test ◽  
On Chip

Weighted Cellular Automata Design for Test Pattern Generator Based on Genetic Algorithm

2013 ◽  
Vol 273 ◽  
pp. 840-844 ◽  
Author(s):  
En Min Tan ◽  
Qing Qing Li ◽  
Ji Gang Jiang
Keyword(s):  
Cellular Automata ◽  
Test Pattern ◽  
Pattern Generator ◽  
Fault Coverage ◽  
Test Design ◽  
Design For Test ◽  
Test Length ◽  
Vlsi Test ◽  
Self Test ◽  
Built In Self Test

In built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test length, fault coverage and test consumption, etc. A one-dimension hybrid cellular automata (CA) is used as the core of test pattern generator, with an optimization of its rules based on multi-objectives evolution algorithm. A certain rule which selected from the optimized rule set is adopted to form the weighted cellular automata, by the using of verilog HDL. Experiment results was obtained by simulation of some ISCAS’8n built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test le5 benchmark circuits, and indicated that the test length was reduced obviously (at a ratio above 60%), without losing fault coverage (within a discrepancy of 3%); moreover, the power consumption would be decreased correspondingly.

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