Modeling switched capacitor sigma delta modulator nonidealities in SystemC-AMS

2010 ◽  
Author(s):  
S. Adhikari ◽  
C. Grimm
Keyword(s):  
Switched Capacitor ◽  
Sigma Delta Modulator ◽  
Sigma Delta

The Design of CIFF Structure Three-Order Switched-Capacitor Sigma-Delta Modulator

2012 ◽  
Vol 433-440 ◽  
pp. 5727-5732
Author(s):  
Jun Han ◽  
Wei Dong Wang
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Optimization Technique ◽  
Cmos Technology ◽  
Switched Capacitor ◽  
Clock Frequency ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Transconductance Amplifier ◽  
A Chain

This paper presents the design and implementation of a single-loop three-order switched-capacitor sigma-delta modulator(SDM) with a standard 0.18um CMOS technology. A current optimization technique is utilized in proposed design to reduce the power of operational transconductance amplifier(OTA).Using a chain of Integrators with weighted feed-forward summation(CIFF) structure and optimized single-stage class-A OTA with positive feed-back to minimize the power consumption. The SDM has been presented with an over-sampling ratio of 128,clock frequency 6.144MHz,24kHz band- width, and achieves a peak SNR of 100dB,103dB dynamic range. The whole circuits consume 2.87mW from a single 1.8V supply voltage.

A RE-CONFIGURABLE ARCHITECTURE FOR SWITCHED CAPACITOR SIGMA-DELTA ANALOG-TO-DIGITAL CONVERSION

2013 ◽  
Vol 22 (09) ◽  
pp. 1340012
Author(s):  
KAREN WAN ◽  
GIGI CHAN ◽  
WILLIAM WONG ◽  
KAM CHUEN WAN ◽  
BRYCE YAU ◽  
...  
Keyword(s):  
Fourth Order ◽  
Cmos Technology ◽  
Second Order ◽  
Switched Capacitor ◽  
Noise Shaping ◽  
Digital Conversion ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Analog To Digital Conversion

A re-configurable switched capacitor sigma-delta analog-to-digital conversion architecture1,2 is proposed. The architecture consists of a MASH sigma delta modulator with nth lower-order (first- or second-order) loops cascaded together. Each loop can be powered on or off operating in high or low performance mode, according to application needs. The architecture can be configured to optimize performance and power consumption for specific resolution and applications. The architecture is proven by means of a prototype, implemented as a fourth-order and fabricated in a standard 0.18 um CMOS technology. The outputs of both high performance mode (fourth-order) and medium performance mode (second-order, first loop ON) are measured to demonstrate the configurability. The FFT demonstrates that the noise shaping for the fourth-order modulator is better than that of the second-order modulator with steeper noise shaping slope.

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