Simultaneous scheduling, allocation and binding in high level synthesis

P. Kollig; B.M. Al-Hashimi

doi:10.1049/el:19971039

Simultaneous scheduling, allocation and binding in high level synthesis

Electronics Letters ◽

10.1049/el:19971039 ◽

1997 ◽

Vol 33 (18) ◽

pp. 1516 ◽

Cited By ~ 16

Author(s):

P. Kollig ◽

B.M. Al-Hashimi

Keyword(s):

High Level Synthesis ◽

High Level ◽

Simultaneous Scheduling

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Parallel algorithms for simultaneous scheduling, binding and floorplanning in high-level synthesis

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187) ◽

10.1109/iscas.1998.705288 ◽

2002 ◽

Cited By ~ 13

Author(s):

P. Prabhakaran ◽

P. Banerjee

Keyword(s):

Parallel Algorithms ◽

High Level Synthesis ◽

High Level ◽

Simultaneous Scheduling

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Simultaneous Scheduling, Allocation, Binding, Re-Ordering, and Encoding for Crosstalk Pattern Minimization During High–Level Synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2009.2031864 ◽

2011 ◽

Vol 19 (2) ◽

pp. 217-226 ◽

Cited By ~ 8

Author(s):

Hariharan Sankaran ◽

Srinivas Katkoori

Keyword(s):

High Level Synthesis ◽

High Level ◽

Simultaneous Scheduling

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Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis

2015 IEEE 11th International Conference on ASIC (ASICON) ◽

10.1109/asicon.2015.7516908 ◽

2015 ◽

Cited By ~ 2

Author(s):

Cong Hao ◽

Jian-Mo Ni ◽

Hui-Tong Wang ◽

Takeshi Yoshimura

Keyword(s):

Complexity Reduction ◽

High Level Synthesis ◽

Resource Usage ◽

High Level ◽

Simultaneous Scheduling

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Simultaneous scheduling, binding and floorplanning in high-level synthesis

Proceedings Eleventh International Conference on VLSI Design ◽

10.1109/icvd.1998.646645 ◽

2002 ◽

Cited By ~ 22

Author(s):

P. Prabhakaran ◽

P. Banerjee

Keyword(s):

High Level Synthesis ◽

High Level ◽

Simultaneous Scheduling

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Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis

2008 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2008.95 ◽

2008 ◽

Cited By ~ 2

Author(s):

Hariharan Sankaran ◽

Srinivas Katkoori

Keyword(s):

High Level Synthesis ◽

High Level ◽

Simultaneous Scheduling

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Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e92.a.3169 ◽

2009 ◽

Vol E92-A (12) ◽

pp. 3169-3179 ◽

Cited By ~ 7

Author(s):

Akira OHCHI ◽

Nozomu TOGAWA ◽

Masao YANAGISAWA ◽

Tatsuo OHTSUKI

Keyword(s):

High Level Synthesis ◽

High Level

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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e100.a.1439 ◽

2017 ◽

Vol E100.A (7) ◽

pp. 1439-1451

Author(s):

Koki IGAWA ◽

Masao YANAGISAWA ◽

Nozomu TOGAWA

Keyword(s):

High Level Synthesis ◽

Synthesis Algorithm ◽

Body Biasing ◽

High Level ◽

Delay Variation

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Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e97.a.2498 ◽

2014 ◽

Vol E97.A (12) ◽

pp. 2498-2506

Author(s):

Akihiro SUDA ◽

Hideki TAKASE ◽

Kazuyoshi TAKAGI ◽

Naofumi TAKAGI

Keyword(s):

High Level Synthesis ◽

Loop Parallelization ◽

Polyhedral Optimization ◽

High Level ◽

Nested Loop

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A parallel ant colony optimization to globally optimize area in high-level synthesis. (c2011)

10.26756/th.2011.36 ◽

2011 ◽

Author(s):

David Elias Kozhaya

Keyword(s):

Ant Colony Optimization ◽

Ant Colony ◽

High Level Synthesis ◽

High Level

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Language requirements for high-level synthesis

10.3403/00837025 ◽

1996 ◽

Keyword(s):

High Level Synthesis ◽

High Level

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