Ultrafast clock recovery technique for high-speed optical packet networks

1995 ◽  
Vol 31 (19) ◽  
pp. 1687-1688 ◽  
Author(s):  
T.K. Fong ◽  
L.G. Kazovsky ◽  
P. Poggiolini ◽  
M. Cerisola ◽  
R.T. Hofmeister
Keyword(s):  
High Speed ◽  
Clock Recovery ◽  
Packet Networks ◽  
Recovery Technique

Analysis of a clock-recovery technique for circuit emulation services over packet networks

2007 ◽  
Vol 21 (1) ◽  
pp. 73-97 ◽  
Author(s):  
James Aweya ◽  
Delfin Y. Montuno ◽  
Michel Ouellette ◽  
Kent Felske
Keyword(s):  
Clock Recovery ◽  
Packet Networks ◽  
Recovery Technique

A High-Speed Low-Voltage Phase Detector for Clock Recovery From NRZ Data

2007 ◽  
Vol 54 (8) ◽  
pp. 1626-1635 ◽  
Author(s):  
Francesco Centurelli ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
High Speed ◽  
Low Voltage ◽  
Clock Recovery ◽  
Phase Detector ◽  
Voltage Phase

High-speed clock recovery unit based on a phase aligner

2003 ◽  
Author(s):  
Efrain Tejera ◽  
Roberto Esper-Chain ◽  
Felix Tobajas ◽  
Valentin De Armas ◽  
Roberto Sarmiento
Keyword(s):  
High Speed ◽  
Clock Recovery ◽  
Recovery Unit

Si Photonics Deployment Using Cu Pillar Interconnect and Chip On Wafer Platform

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001663-001681
Author(s):  
Miguel Jimarez
Keyword(s):  
Light Source ◽  
Silicon Photonics ◽  
High Speed ◽  
High Sensitivity ◽  
Optical Path ◽  
Clock Recovery ◽  
Wafer Scale ◽  
Si Photonics ◽  
Cu Pillar ◽  
Fine Pitch

We introduce a high-speed 4x25Gbps, MSA-compliant, QSFP transceiver built on a Silicon Photonics platform. The transceiver integrates high sensitivity receivers, CTLE, clock recovery, modulator drivers and BIST on a TSMC 28nm die connected to the photonic die thru a fine pitch (50um) Copper Pillar interface. A wafer-scale approach, Chip on Wafer, CoW, is used to assemble the electronic die and the light source on to the photonic die, so that the full optical path can be tested, at speed, in loopback configuration in wafer form, using a standard ATE solution. This presentation focuses on the CoW assembly development aspects of the transceiver. Wafer probe and bump, die processing services, CoW assembly and Back End of Line, BEOL, Test Services will be presented.

scholarly journals Design of High frequency Voltage Controlled Oscillators for Phase Locked Loop

2018 ◽  
Vol 7 (3.12) ◽  
pp. 871
Author(s):  
Thejusraj. H ◽  
Prithivi Raj ◽  
J Selvakumar ◽  
S Praveen Kumar
Keyword(s):  
Power Consumption ◽  
High Frequency ◽  
High Speed ◽  
Phase Locked Loop ◽  
Clock Recovery ◽  
Ring Oscillator ◽  
Voltage Controlled Oscillator ◽  
Voltage Controlled Oscillators ◽  
Clock Generation ◽  
Consumption Values

This paper presents the analysis of various oscillators that generate high frequency of oscillation for high speed communication, clock generation and clock recovery. The Ring oscillator and the Current Starved Voltage Controlled Oscillator(CSVCO) (for 5-stagewithout resistor and with resistor) have been implemented using the Cadence Virtuoso tool in 90 nm technology. The generated frequency of oscillation and the power consumption values of the voltage controlled oscillators have been calculated after inclusion in the PLL, and were also compared to identify the most suitable voltage controlled oscillator for a given application.

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