Fully time-division-multiplexed 100 Gbit/s optical transmission experiment

1993 ◽  
Vol 29 (25) ◽  
pp. 2211 ◽  
Author(s):  
S. Kawanishi ◽  
H. Takara ◽  
K. Uchiyama ◽  
M. Saruwatari ◽  
T. Kitoh
1996 ◽  
Vol 32 (5) ◽  
pp. 470 ◽  
Author(s):  
S. Kawanishi ◽  
H. Takara ◽  
O. Kamatani ◽  
T. Morioka ◽  
M. Saruwatari

1995 ◽  
Vol 31 (10) ◽  
pp. 816-817 ◽  
Author(s):  
S. Kawanishi ◽  
T. Morioka ◽  
O. Kamatani ◽  
H. Takara ◽  
M. Saruwatari

2003 ◽  
Vol 13 (01) ◽  
pp. 239-263
Author(s):  
T. MASUDA ◽  
N. SHIRAMIZU ◽  
E. OHUE ◽  
K. ODA ◽  
R. HAYAMI ◽  
...  

Using a 0.2-μm self-aligned epitaxial-growth silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technology, we have developed a chipset for 40-Gb/s time-division multiplexing optical transmission systems. In this paper, we describe seven analog and digital ICs: a 45-GHz bandwidth transimpedance amplifier, a 48.7-GHz bandwidth automatic-gain-controllable amplifier, a 40-Gb/s decision circuit, a 40-Gb/s full-wave rectifier, a 40-Gb/s limiting amplifier with a 32-dB gain, a 45-Gb/s 1:4 demultiplexer, and a 45-Gb/s 4:1 multiplexer. To increase bandwidth of the transimpedance amplifier, a common-base input stage is introduced. In order to have high gain and wide bandwidth simultaneously, active load circuits composed of a differential transimpedance amplifier are used for the AGC amplifier, the limiting amplifier, and the decision circuit. Full-rate clocking is employed to reduce the influence caused by clock-duty variation in digital circuits such as the decision circuit, the demultiplexer, and the multiplexer. All ICs were characterized by using on-wafer probes, and some of them were built in brass-packages for bit-error rate measurement.


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