High-speed GaAs 4×4-bit parallel multiplier using super capacitor FET logic

1987 ◽  
Vol 23 (8) ◽  
pp. 425
Author(s):  
K.S. Lowe
Keyword(s):  
High Speed ◽  
Super Capacitor ◽  
Parallel Multiplier

scholarly journals VLSI ARCHITECTURE OF PARALLEL MULTIPLIER– ACCUMULATOR BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM

2012 ◽  
pp. 40-46
Author(s):  
Mr.M.V. Sathish ◽  
Mrs. Sailaja
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
High Performance ◽  
Vlsi Architecture ◽  
Clock Frequency ◽  
Parallel Multiplier ◽  
Hybrid Type ◽  
Standard Design ◽  
Overall Performance ◽  
And Performance

A new architecture of multiplier-andaccumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposing method CSA tree uses 1’s-complement-based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency. We expect that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas.

A high-speed LSI GaAs 8x8 bit parallel multiplier

1982 ◽  
Vol 17 (4) ◽  
pp. 638-647 ◽  
Author(s):  
F.S. Lee ◽  
G.R. Kaelin ◽  
B.M. Welch ◽  
R. Zucca ◽  
E. Shen ◽  
...  
Keyword(s):  
High Speed ◽  
Parallel Multiplier

A high-speed high-density silicon 8×8-bit parallel multiplier

1987 ◽  
Vol 22 (1) ◽  
pp. 35-40 ◽  
Author(s):  
J.Y. Lee ◽  
H.L. Garvin ◽  
C.W. Slayman
Keyword(s):  
High Speed ◽  
High Density ◽  
Parallel Multiplier

Low-Power and Area-Efficient Parallel Multiplier Design Using Two-Dimensional Bypassing

2016 ◽  
Vol 26 (02) ◽  
pp. 1750030 ◽  
Author(s):  
Pankaj Kumar ◽  
Rajender Kumar Sharma
Keyword(s):  
Signal Processing ◽  
Low Power ◽  
High Speed ◽  
Digital Signal ◽  
Cmos Technology ◽  
Two Dimensional ◽  
Efficient Design ◽  
Parallel Multiplier ◽  
Power Delay Product ◽  
Area Efficient

To develop low-power, high-speed and area-efficient design for portable electronics devices and signal processing applications is a very challenging task. Multiplier has an important role in digital signal processing. Reducing the power consumption of multiplier will bring significant power reduction and other associated advantages in the overall digital system. In this paper, a low-power and area-efficient two-dimensional bypassing multiplier is presented. In two-dimensional bypassing, row and column are bypassed and thus the switching power is saved. Simulation results are realized using UMC 90[Formula: see text]nm CMOS technology and 0.9[Formula: see text]V, with Cadence Spectre simulation tool. The proposed architecture is compared with the existing multiplier architectures, i.e., Braun’s multiplier, row bypassing multiplier, column bypassing multiplier and row and column bypassing multiplier. Performance parameters of the proposed multiplier are better than the existing multipliers in terms of area occupation, power dissipation and power-delay product. These results are obtained for randomly generated input test patterns having uniform distribution probability.

A HIGH SPEED ARITHMETIC ARCHITECTURE OF PARALLEL MULTIPLIER-ACCUMULATOR (MAC) BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM

2017 ◽  
Vol 5 (3) ◽  
pp. 38
Author(s):  
VERMA ISHITA ◽  
GHOSH PRIYANKA ◽  
SONI UPENDRA ◽  
SINGH DHARMENDRA ◽  
◽  
...  
Keyword(s):  
High Speed ◽  
Parallel Multiplier
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