Floating substrate effects on speed performance in scaled CMOS/SOS circuits

1986 ◽  
Vol 22 (4) ◽  
pp. 177 ◽  
Author(s):  
H. Hatano
Keyword(s):  
Substrate Effects ◽  
Speed Performance ◽  
Scaled Cmos

Laser Silicon Interaction Study on Ring Oscillators to Establish Temperature Voltage Dependency Trends on 14 nm and Future FinFET Technologies

2017 ◽  
Author(s):  
Gaurav Mattey ◽  
Lava Ranganathan
Keyword(s):  
High Speed ◽  
Laser Frequency ◽  
Ring Oscillator ◽  
Switching Speed ◽  
Dual Nature ◽  
Voltage Imaging ◽  
Multiple Cores ◽  
Speed Performance ◽  
Self Test ◽  
Frequency Changes

Abstract Critical speed path analysis using Dynamic Laser Stimulation (DLS) technique has been an indispensable technology used in the Semiconductor IC industry for identifying process defects, design and layout issues that limit product speed performance. Primarily by injecting heat or injecting photocurrent in the active diffusion of the transistors, the laser either slows down or speeds up the switching speed of transistors, thereby affecting the overall speed performance of the chip and revealing the speed limiting/enhancing circuits. However, recently on Qualcomm Technologies’ 14nm FinFET technology SOC product, the 1340nm laser’s heating characteristic revealed a Vt (threshold voltage) improvement behavior at low operating voltages which helped identify process issues on multiple memory array blocks across multiple cores failing for MBIST (Memory Built-in Self-test). In this paper, we explore the innovative approach of using the laser to study Vt shifts in transistors due to process issues. We also study the laser silicon interactions through scanning the 1340nm thermal laser on silicon and observing frequency shifts in a high-speed Ring Oscillator (RO) on 16nm FinFET technology. This revealed the normal and reverse Temperature Dependency Gate voltages for 16nm FinFET, thereby illustrating the dual nature of stimulation (reducing mobility and improving Vt) from a thermal laser. Frequency mapping through Laser Voltage Imaging (LVI) was performed on the Ring Oscillator (RO) using the 1340nm thermal laser, while concurrently stimulating the transistors of the RO. Spatial distribution of stimulation was studied by observing the frequency changes on LVI.

Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier

2019 ◽  
Vol 13 (2) ◽  
pp. 174-180
Author(s):  
Poonam Sharma ◽  
Ashwani Kumar Dubey ◽  
Ayush Goyal
Keyword(s):  
Image Processing ◽  
High Speed ◽  
Computation Time ◽  
Digital Signal ◽  
Instruction Set ◽  
Computationally Efficient ◽  
Specific Instruction ◽  
Processor Core ◽  
Speed Performance ◽  
Application Specific

Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.

scholarly journals Substrate effects and evaluation of elastic moduli of components of inhomogeneous films by nanoindentation

2016 ◽  
Vol 619 ◽  
pp. 112-119 ◽  
Author(s):  
E.L. Kossovich ◽  
F.M. Borodich ◽  
S.J. Bull ◽  
S.A. Epshtein
Keyword(s):  
Elastic Moduli ◽  
Substrate Effects

Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities

2021 ◽  
Vol 29 (5) ◽  
pp. 843-856
Author(s):  
Sriram Vangal ◽  
Somnath Paul ◽  
Steven Hsu ◽  
Amit Agarwal ◽  
Saurabh Kumar ◽  
...  
Keyword(s):  
Wide Range ◽  
Challenges And Opportunities ◽  
Many Core ◽  
Scaled Cmos

scholarly journals Investigative analysis of match-line sensing schemes in TCAM for high-speed performance

2021 ◽  
Vol 1045 (1) ◽  
pp. 012040
Author(s):  
Fahim Faisal ◽  
Mirza Muntasir Nishat ◽  
Sayka Afreen Mim ◽  
Hafsa Akter ◽  
Md. Rafid Kaysar Shagor
Keyword(s):  
High Speed ◽  
Speed Performance

Substrate effects on electrical parameters of Dirac fermions in graphene

2021 ◽  
Vol 133 ◽  
pp. 105936
Author(s):  
E. Tiras ◽  
S. Ardali ◽  
H.A. Firat ◽  
E. Arslan ◽  
E. Ozbay
Keyword(s):  
Dirac Fermions ◽  
Electrical Parameters ◽  
Substrate Effects
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