Reconfigurable 2, 3 and 5‐point DFT processing element for SDF FFT architecture using fast cyclic convolution algorithm

Bibin Sam Paul S.; A.X. Glittas; M. Sellathurai; G. Lakshminarayanan

doi:10.1049/el.2019.4262

Reconfigurable 2, 3 and 5‐point DFT processing element for SDF FFT architecture using fast cyclic convolution algorithm

Electronics Letters ◽

10.1049/el.2019.4262 ◽

2020 ◽

Vol 56 (12) ◽

pp. 592-594

Author(s):

Bibin Sam Paul S. ◽

A.X. Glittas ◽

M. Sellathurai ◽

G. Lakshminarayanan

Keyword(s):

Processing Element ◽

Cyclic Convolution ◽

Convolution Algorithm

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A novel derivation of the Agarwal-Cooley fast cyclic convolution algorithm based on the Good-Thomas Prime Factor algorithm

38th Midwest Symposium on Circuits and Systems. Proceedings ◽

10.1109/mwscas.1995.504385 ◽

2002 ◽

Author(s):

M. Teixeira ◽

D. Rodriguez

Keyword(s):

Prime Factor ◽

Cyclic Convolution ◽

Convolution Algorithm ◽

Prime Factor Algorithm

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Cyclic Convolution Algorithm Formulations Using Polynomial Transform Theory

Journal of Computers ◽

10.4304/jcp.2.7.40-48 ◽

2007 ◽

Vol 2 (7) ◽

Author(s):

Abraham H. Diaz-Perez ◽

Domingo Rodriguez

Keyword(s):

Cyclic Convolution ◽

Convolution Algorithm ◽

Polynomial Transform

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An RNS Implementation of a Length-8 DCT Based on a Cyclic Convolution Algorithm

Signal Processing ◽

10.1016/b978-0-444-89587-5.50091-8 ◽

1992 ◽

pp. 1553-1556

Author(s):

S. Wolter ◽

R. Laur

Keyword(s):

Cyclic Convolution ◽

Convolution Algorithm

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Implementation of Novel Parallel Cyclic Convolution Algorithms in Clusters and Multi-Core Architectures

10.21236/ada614062 ◽

2014 ◽

Author(s):

Marvi Teixeira ◽

Felix Nevarez

Keyword(s):

Cyclic Convolution

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Design and implementation of a GaAs systolic floating-point processing element

IEE Proceedings - Computers and Digital Techniques ◽

10.1049/ip-cdt:19960635 ◽

1996 ◽

Vol 143 (5) ◽

pp. 325

Author(s):

A. Beaumont-Smith ◽

W. Marwood ◽

C.C. Lim ◽

K. Eshraghian

Keyword(s):

Processing Element ◽

Floating Point ◽

Design And Implementation

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Buffer Controller-Based Multiple Processing Element Utilization for Dataflow Synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2010.2049388 ◽

2011 ◽

Vol 19 (7) ◽

pp. 1249-1262 ◽

Cited By ~ 1

Author(s):

Woohyung Chun ◽

Sungroh Yoon ◽

Sangjin Hong

Keyword(s):

Processing Element ◽

Multiple Processing

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Generalization of the cyclic convolution system and its applications

2000 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.00CH37100) ◽

10.1109/icassp.2000.860118 ◽

2002 ◽

Cited By ~ 3

Author(s):

H. Murakami

Keyword(s):

Cyclic Convolution

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A floating-point systolic array processing element with serial communication and built-in self-test

The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology ◽

10.1007/bf02106449 ◽

1994 ◽

Vol 8 (3) ◽

pp. 241-251

Author(s):

T. C. Davies ◽

D. Al-Khalili ◽

V. Szwarc

Keyword(s):

Systolic Array ◽

Array Processing ◽

Serial Communication ◽

Processing Element ◽

Floating Point ◽

Self Test ◽

Built In Self Test

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Design of fast fourier transform using processing element for real valued signal

2015 International Conference on Communications and Signal Processing (ICCSP) ◽

10.1109/iccsp.2015.7322752 ◽

2015 ◽

Cited By ~ 1

Author(s):

Ankush R. Kuralkar

Keyword(s):

Fourier Transform ◽

Fast Fourier Transform ◽

Processing Element

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A novel coarse grain reconfigurable processing element architecture

2003 46th Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.2003.1562414 ◽

2006 ◽

Cited By ~ 3

Author(s):

A. Happonen ◽

E. Hemming ◽

M.J. Juntti

Keyword(s):

Processing Element ◽

Coarse Grain ◽

Reconfigurable Processing

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