scholarly journals Pole‐to‐ground fault current estimation in symmetrical monopole high‐voltage direct current grid considering modular multilevel converter control

2020 ◽  
Vol 56 (8) ◽  
pp. 392-395
Author(s):  
Yan Tao ◽  
Baohong Li ◽  
Tianqi Liu
2019 ◽  
Vol 9 (8) ◽  
pp. 1661 ◽  
Author(s):  
Kaipei Liu ◽  
Qing Huai ◽  
Liang Qin ◽  
Shu Zhu ◽  
Xiaobing Liao ◽  
...  

The main weakness of the half-bridge modular multilevel converter-based high-voltage direct current (MMC-HVDC) system lies in its immature solution to extremely high current under direct current (DC) line fault. The development of the direct current circuit breaker (DCCB) remains constrained in terms of interruption capacity and operation speed. Therefore, it is essential to limit fault current in the MMC-HVDC system. An enhanced fault current-limiting circuit (EFCLC) is proposed on the basis of fault current study to restrict fault current under DC pole-to-pole fault. Specifically, the EFCLC consists of fault current-limiting inductance L F C L and energy dissipation resistance R F C L in parallel with surge arrestor. L F C L reduces the fault current rising speed, together with arm inductance and smoothing reactor. However, in contrast to arm inductance and smoothing reactor, L F C L will be bypassed via parallel-connected thyristors after blocking converter to prevent the effect on fault interruption speed. R F C L shares the stress on energy absorption device (metal oxide arrester) to facilitate fault interruption. The DCCB requirement in interruption capacity and breaking speed can be satisfied effortlessly through the EFCLC. The working principle and parameter determination of the EFCLC are presented in detail, and its effectiveness is verified by simulation in RT-LAB and MATLAB software platforms.


Author(s):  
Araitz Iturregi ◽  
Agurtzane Etxegarai ◽  
D. Marene Larruskain ◽  
Pablo Eguia ◽  
Oihane Abarrategui

Goi-tentsioko korronte zuzeneko (ingelesez, High Voltage Direct Current HVDC) garraio-sistemak gero eta garrantzitsuagoak dira sistema elektrikoan, onura ekonomiko eta teknikoak direla eta. Hala ere, akatsen bat gertatzen denean, korrontea eteteak oraindik ere erronka izaten jarraitzen du HVDC sareetan. Desiragarriak ez diren korronteak eteteko, korronte zuzeneko etengailuak erabil daitezke, baina horien gaitasuna mugatua da. Egoera hala izanik, akats-korronteen mugagailuak (ingelesez, Fault Current Limiter FCL) dira proposamenik egokiena akats-korronteak maneiagarriagoak diren balioetara txikitzeko; hartara, sistema elektrikoaren garraio-ahalmena handitu daiteke, ekipamendua aldatu beharrik gabe. Sarean aldez aurretik legokeen ekipamendua gai izango litzateke korronte berriak kudeatzeko eta sistema era eraginkorrean babesteko FCLen erabilpenaz. Artikulu honetan, FCL tresnen ezaugarri orokorrak eta sailkapena aurkezten dira. Ondoren, egoera solidoko FCLa erabili da maila anizkoitzeko bihurgailudun (ingelesez, Modular Multilevel Converter MMC) VSC-HVDC (ingelesez, Voltage Source Converter) sistema batean, eta horren jokaera azaltzen da simulazio bidez.


2020 ◽  
Author(s):  
◽  
Sindisiwe Cindy Malanda

A multiterminal HVDC system includes the connection of different HVDC terminals to a common grid. Most of the MTDC networks are realized in voltage source converter (VSC) high voltage direct current (HVDC). Over long distances, HVDC transmission is preferred to high voltage direct current (HVAC). Furthermore, HVDC is subjected to minimal harmonics oscillation problems due to the absence of frequency. HVDC enables the interconnection of systems at different frequencies, and the system becomes free of angular stability problems. VSCs employ insulated gate bipolar transistors (IGBTs) switches, and High-frequency pulse width modulation is used to operate the IGBTs in order to achieve high-speed control of active and reactive power. The growth of MTDC networks may require a new type of VSCs topology, which is resilient and efficient to dc and ac network fault. This research investigation focuses on the transient dc-side fault analysis in a two-level Monopolar VSC- Based Multi-Terminal HVDC Scheme consisting of four asynchronous terminals sharing a rated 400kV DC-grid was carried out in PSCAD software. During dc-side fault analysis, a pole-to-ground fault was taken into consideration as it’s more likely to occur, although it is less severe compared to pole-to-pole. The converters are interconnected through 100 km dc cables placed 0.5 gm apart and at a depth of 1.5 m underground. It was observed that during the steady-state analysis, the dc voltage in the grid was maintained at the rated value 400 kV, the currents measured at the converters bus was 0.5 kA, and the current flowing through the cables was 0.25 kA. Under the fault condition, the dc voltage drop needs to be maintained to a closed range to avoid the grid to collapse. The voltage droop technique was incorporated in the dc voltage controller to keep the dc voltage at the narrow range. Depending on the value and nature of ground fault resistance, the fault current magnitude varies, and distance variation along the cable has a significant contribution in the fault current. It is observed that fault close to the converter (5 km’s measured 9 kA) results in high fault currents compared to fault away from the converter (50 km’s measured 7.8 kA). The protection design of the VSC needs to be able to detect whether its ground fault or short circuit since the location of the fault needs to be identified and repaired. Another observation made when the fault is inserted 50 kms away from the converter, meaning the fault is at the center of the two converters, the outcome results in high currents in both converters. The isolation of the fault should be fast and selective as the critical time is very short. The dc circuit breakers are mostly recommended to be used as primary protection; however, different protection techniques need to be incorporated with dc circuit breaker in order to quickly identify, select and reliable isolate the faulted line. Moreover, the protection should be able to isolate the line before the fault reaches the maximum fault current to avoid the damage in the converter components.


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