scholarly journals Advanced layout techniques for high‐speed analogue circuits in 28 nm HKMG CMOS process

2018 ◽  
Vol 54 (8) ◽  
pp. 486-488 ◽  
Author(s):  
F. Meng ◽  
K. Li ◽  
D.J. Thomson ◽  
P. Wilson ◽  
G.T. Reed
Keyword(s):  
High Speed ◽  
Cmos Process ◽  
Analogue Circuits ◽  
28 Nm

scholarly journals A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1873
Author(s):  
Chen Cai ◽  
Xuqiang Zheng ◽  
Yong Chen ◽  
Danyu Wu ◽  
Jian Luan ◽  
...  
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Data Rate ◽  
Quality Data ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Feed Forward ◽  
Fully Integrated ◽  
Output Driver ◽  
28 Nm

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane's data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

High Speed 1-tap Decision Feedback Equalizer in 28 nm CMOS

2014 ◽  
Vol 9 (9th) ◽  
pp. 1-12
Author(s):  
Mostafa Hosny ◽  
Sameh Ibrahim ◽  
DiaaEldin Khalil ◽  
Mohamed Dessouky
Keyword(s):  
High Speed ◽  
Decision Feedback ◽  
Decision Feedback Equalizer ◽  
28 Nm

A High-Speed Temperature Sensor with Low Supply Sensitivity for SoC Thermal Monitoring

2018 ◽  
Vol 27 (07) ◽  
pp. 1850116
Author(s):  
Yuanxin Bao ◽  
Wenyuan Li
Keyword(s):  
Temperature Sensor ◽  
Conversion Rate ◽  
High Speed ◽  
Supply Voltage ◽  
Ring Oscillator ◽  
Temperature Sensitive ◽  
Cmos Process ◽  
Digital Code ◽  
Thermal Monitoring ◽  
Worst Case

A high-speed low-supply-sensitivity temperature sensor is presented for thermal monitoring of system on a chip (SoC). The proposed sensor transforms the temperature to complementary to absolute temperature (CTAT) frequency and then into digital code. A CTAT voltage reference supplies a temperature-sensitive ring oscillator, which enhances temperature sensitivity and conversion rate. To reduce the supply sensitivity, an operational amplifier with a unity gain for power supply is proposed. A frequency-to-digital converter with piecewise linear fitting is used to convert the frequency into the digital code corresponding to temperature and correct nonlinearity. These additional characteristics are distinct from the conventional oscillator-based temperature sensors. The sensor is fabricated in a 180[Formula: see text]nm CMOS process and occupies a small area of 0.048[Formula: see text]mm2 excluding bondpads. After a one-point calibration, the sensor achieves an inaccuracy of [Formula: see text][Formula: see text]1.5[Formula: see text]C from [Formula: see text]45[Formula: see text]C to 85[Formula: see text]C under a supply voltage of 1.4–2.4[Formula: see text]V showing a worst-case supply sensitivity of 0.5[Formula: see text]C/V. The sensor maintains a high conversion rate of 45[Formula: see text]KS/s with a fine resolution of 0.25[Formula: see text]C/LSB, which is suitable for SoC thermal monitoring. Under a supply voltage of 1.8[Formula: see text]V, the maximum energy consumption per conversion is only 7.8[Formula: see text]nJ at [Formula: see text]45[Formula: see text]C.

scholarly journals A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 68
Author(s):  
Woorham Bae ◽  
Sung-Yong Cho ◽  
Deog-Kyoon Jeong
Keyword(s):  
Finite Impulse Response ◽  
Cmos Process ◽  
Pci Express ◽  
Fully Integrated ◽  
Peripheral Component Interconnect ◽  
Low Power Cmos ◽  
On Chip ◽  
Output Driver ◽  
Wide Operating ◽  
28 Nm

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

scholarly journals A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2260
Author(s):  
Khuram Shehzad ◽  
Deeksha Verma ◽  
Danial Khan ◽  
Qurat Ul Ain ◽  
Muhammad Basim ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Intelligent Transportation System ◽  
Cmos Process ◽  
Process Technology ◽  
Back Issue ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Switching Method

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

LOW-POWER, PARALLEL INTERFACE WITH CONTINUOUS-TIME ADAPTIVE PASSIVE EQUALIZER AND CROSSTALK CANCELLATION

2005 ◽  
Vol 15 (02) ◽  
pp. 459-476
Author(s):  
C. PATRICK YUE ◽  
JAEJIN PARK ◽  
RUIFENG SUN ◽  
L. RICK CARLEY ◽  
FRANK O'MAHONY
Keyword(s):  
Low Power ◽  
Electromagnetic Interference ◽  
Continuous Time ◽  
High Speed ◽  
High Performance ◽  
Process Variations ◽  
Cmos Process ◽  
Power Circuit ◽  
Crosstalk Cancellation ◽  
Circuit Components

This paper presents the low-power circuit techniques suitable for high-speed digital parallel interfaces each operating at over 10 Gbps. One potential application for such high-performance I/Os is the interface between the channel IC and the magnetic read head in future compact hard disk systems. First, a crosstalk cancellation technique using a novel data encoding scheme is introduced to suppress electromagnetic interference (EMI) generated by the adjacent parallel I/Os . This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-μm digital CMOS process, the transceiver consumes 310 mW per 10-Gps channel from a I-V supply based on simulation results. Next, a 20-Gbps continuous-time adaptive passive equalizer utilizing on-chip lumped RLC components is described. Passive equalizers offer the advantages of higher bandwidth and lower power consumption compared with conventional designs using active filter. A low-power, continuous-time servo loop is designed to automatically adjust the equalizer frequency response for the optimal gain compensation. The equalizer not only adapts to different channel characteristics, but also accommodates temperature and process variations. Implemented in a 0.25-μm, 1P6M BiCMOS process, the equalizer can compensate up to 20 dB of loss at 10 GHz while only consumes 32 mW from a 2.5-V supply.

ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process

2007 ◽  
Author(s):  
Yuan-Wen Hsiao ◽  
Ming-Dou Ker ◽  
Po-Yen Chiu ◽  
Chun Huang ◽  
Yuh-Kuang Tseng
Keyword(s):  
High Speed ◽  
Cmos Process ◽  
Esd Protection

scholarly journals Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 369 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Nikos Mastorakis
Keyword(s):  
High Speed ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Performance Comparison ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Least Significant Bit ◽  
Design Metrics ◽  
Ripple Carry Adder ◽  
Speed Performance

Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing binary-to-excess-1 code (BEC) converters. In the literature, the designs of many CLAs and CSLAs were described separately. It would be useful to have a direct comparison of their performances based on the design metrics. Hence, we implemented homogeneous and hybrid CLAs, and CSLAs with and without the BEC converters by considering 32-bit accurate and approximate additions to facilitate a comparison. For the gate-level implementations, we considered a 32/28 nm complementary metal-oxide-semiconductor (CMOS) process targeting a typical-case process–voltage–temperature (PVT) specification. The results show that the hybrid CLA/RCA architecture is preferable among the CLA and CSLA architectures from the speed and power perspectives to perform accurate and approximate additions.

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