High‐speed transimpedance amplifier with runtime adaptive bandwidth and power consumption in 0.13 μm SiGe BiCMOS

2016 ◽  
Vol 52 (2) ◽  
pp. 154-156 ◽  
Author(s):  
D. Schoeniger ◽  
R. Henker ◽  
F. Ellinger
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Transimpedance Amplifier ◽  
Sige Bicmos ◽  
Adaptive Bandwidth

MULTI-GHzSiGe BiCMOS FPGAs WITH NEW ARCHITECTURE AND NOVEL POWER MANAGEMENT TECHNIQUES

2005 ◽  
Vol 14 (02) ◽  
pp. 179-193 ◽  
Author(s):  
K. ZHOU ◽  
J.-R. GUO ◽  
C. YOU ◽  
J. MAYEGA ◽  
R. P. KRAFT ◽  
...  
Keyword(s):  
Power Consumption ◽  
Power Management ◽  
Silicon Germanium ◽  
High Speed ◽  
Management Scheme ◽  
Sige Bicmos ◽  
Field Programmable ◽  
Speed Advantage ◽  
Low Power Cmos ◽  
Programmable Gate Arrays

The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened a door for GHz Field Programmable Gate Arrays (FPGAs).1,2 The integration of high-speed SiGe HBTs and low-power CMOS gives a significant speed advantage to SiGe FPGAs over CMOS FPGAs. In the past, high static power consumption discouraged the pursuit of bipolar FPGAs from being scaled up significantly. This paper details new ideas to reduce power in designing high-speed SiGe BiCMOS FPGAs. The paper explains new methods to reduce circuitry and utilize a novel power management scheme to achieve a flexible trade-off between power consumption and circuit speed. In addition, new decoding logic is developed with shared address and data lines. A SiGe FPGA test chip based on the Xilinx 6200 architecture has been fabricated for demonstration.

A BiCMOS 120 mW 11 GHz TRANSIMPEDANCE AMPLIFIER DEDICATED FOR HIGH-SPEED PHOTORECEIVERS

2006 ◽  
Vol 15 (04) ◽  
pp. 467-490
Author(s):  
ANDRÉ BOYOGUÉNO ◽  
MOHAMAD SAWAN ◽  
MUSTAPHA SLAMANI
Keyword(s):  
High Speed ◽  
Low Noise ◽  
Transimpedance Amplifier ◽  
Dc Offset ◽  
Text Input ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Offset Compensation ◽  
On Chip ◽  
Conversion Scheme

We present a new low-noise, low-power SiGe transimpedance amplifier (TIA) by combining an automatic DC photo-current cancellation, an on-chip DC offset compensation circuit and a single-ended to differential conversion scheme. The conversion method is based of the replica biasing technique in order to provide balanced output signals to the subsequent stages. The chip was fabricated in a 0.18 μm SiGe BiCMOS technology. Experimental results show excellent performances such as 11 GHz bandwidth, 75-dBΩ transimpedance, -19.2 dBm sensitivity measured at 10 Gb/s at a Bit Error Rate (BER) of 10-12, [Formula: see text] input referred noise, and 9.5 ps peak-to-peak jitter which are the best overall performances reported in its category. The photoreceiver chip is expected to dissipate only 120 mW from a single 3.3 V power supply.

Design and Implementation of an Efficient Parallel LFSR Architecture for Wireless Communication Systems

2019 ◽  
Vol 14 ◽  
Author(s):  
A. Suresh Babu ◽  
B. Anand
Keyword(s):  
Wireless Communication ◽  
Power Consumption ◽  
Low Power ◽  
Communication Systems ◽  
High Speed ◽  
Design Tool ◽  
Shift Register ◽  
Linear Feedback ◽  
Wireless Communication Systems ◽  
Coverage Area

: A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals CFD Simulation of a Hyperloop Capsule Inside a Low-Pressure Environment Using an Aerodynamic Compressor as Propulsion and Drag Reduction Method

2021 ◽  
Vol 11 (9) ◽  
pp. 3934
Author(s):  
Federico Lluesma-Rodríguez ◽  
Temoatzin González ◽  
Sergio Hoyas
Keyword(s):  
Shock Waves ◽  
Power Consumption ◽  
High Speed ◽  
Cfd Simulation ◽  
Aerodynamic Drag ◽  
Flow Behavior ◽  
Critical Conditions ◽  
Vehicle Speed ◽  
Blockage Ratio ◽  
The Cost

One of the most restrictive conditions in ground transportation at high speeds is aerodynamic drag. This is even more problematic when running inside a tunnel, where compressible phenomena such as wave propagation, shock waves, or flow blocking can happen. Considering Evacuated-Tube Trains (ETTs) or hyperloops, these effects appear during the whole route, as they always operate in a closed environment. Then, one of the concerns is the size of the tunnel, as it directly affects the cost of the infrastructure. When the tube size decreases with a constant section of the vehicle, the power consumption increases exponentially, as the Kantrowitz limit is surpassed. This can be mitigated when adding a compressor to the vehicle as a means of propulsion. The turbomachinery increases the pressure of part of the air faced by the vehicle, thus delaying the critical conditions on surrounding flow. With tunnels using a blockage ratio of 0.5 or higher, the reported reduction in the power consumption is 70%. Additionally, the induced pressure in front of the capsule became a negligible effect. The analysis of the flow shows that the compressor can remove the shock waves downstream and thus allows operation above the Kantrowitz limit. Actually, for a vehicle speed of 700 km/h, the case without a compressor reaches critical conditions at a blockage ratio of 0.18, which is a tunnel even smaller than those used for High-Speed Rails (0.23). When aerodynamic propulsion is used, sonic Mach numbers are reached above a blockage ratio of 0.5. A direct effect is that cases with turbomachinery can operate in tunnels with blockage ratios even 2.8 times higher than the non-compressor cases, enabling a considerable reduction in the size of the tunnel without affecting the performance. This work, after conducting bibliographic research, presents the geometry, mesh, and setup. Later, results for the flow without compressor are shown. Finally, it is discussed how the addition of the compressor improves the flow behavior and power consumption of the case.

Circuit-Level Safe-Operating-Area of a High-Speed SiGe BiCMOS Wireline Driver

2020 ◽  
Author(s):  
Arya Moradinia ◽  
Rafael P. Martinez ◽  
Jeffrey W. Teng ◽  
Nelson Sepulveda-Ramos ◽  
Harrison Lee ◽  
...  
Keyword(s):  
High Speed ◽  
Sige Bicmos ◽  
Safe Operating

scholarly journals Towards an Efficient CNN Inference Architecture Enabling In-Sensor Processing

Sensors ◽  
2021 ◽  
Vol 21 (6) ◽  
pp. 1955
Author(s):  
Md Jubaer Hossain Pantho ◽  
Pankaj Bhowmik ◽  
Christophe Bobda
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Image Sensor ◽  
Machine Learning Algorithms ◽  
Hierarchical Optimization ◽  
Computation Method ◽  
Optimization Approach ◽  
Efficient Computation ◽  
Feature Maps ◽  
Dynamic Power

The astounding development of optical sensing imaging technology, coupled with the impressive improvements in machine learning algorithms, has increased our ability to understand and extract information from scenic events. In most cases, Convolution neural networks (CNNs) are largely adopted to infer knowledge due to their surprising success in automation, surveillance, and many other application domains. However, the convolution operations’ overwhelming computation demand has somewhat limited their use in remote sensing edge devices. In these platforms, real-time processing remains a challenging task due to the tight constraints on resources and power. Here, the transfer and processing of non-relevant image pixels act as a bottleneck on the entire system. It is possible to overcome this bottleneck by exploiting the high bandwidth available at the sensor interface by designing a CNN inference architecture near the sensor. This paper presents an attention-based pixel processing architecture to facilitate the CNN inference near the image sensor. We propose an efficient computation method to reduce the dynamic power by decreasing the overall computation of the convolution operations. The proposed method reduces redundancies by using a hierarchical optimization approach. The approach minimizes power consumption for convolution operations by exploiting the Spatio-temporal redundancies found in the incoming feature maps and performs computations only on selected regions based on their relevance score. The proposed design addresses problems related to the mapping of computations onto an array of processing elements (PEs) and introduces a suitable network structure for communication. The PEs are highly optimized to provide low latency and power for CNN applications. While designing the model, we exploit the concepts of biological vision systems to reduce computation and energy. We prototype the model in a Virtex UltraScale+ FPGA and implement it in Application Specific Integrated Circuit (ASIC) using the TSMC 90nm technology library. The results suggest that the proposed architecture significantly reduces dynamic power consumption and achieves high-speed up surpassing existing embedded processors’ computational capabilities.

scholarly journals A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2260
Author(s):  
Khuram Shehzad ◽  
Deeksha Verma ◽  
Danial Khan ◽  
Qurat Ul Ain ◽  
Muhammad Basim ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Intelligent Transportation System ◽  
Cmos Process ◽  
Process Technology ◽  
Back Issue ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Switching Method

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

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