Curvature‐corrected low‐noise sub‐bandgap reference in 28 nm CMOS technology

2014 ◽  
Vol 50 (5) ◽  
pp. 396-398 ◽  
Author(s):  
D.F. Bowers ◽  
E.J. Modica
Keyword(s):  
Cmos Technology ◽  
Low Noise ◽  
Bandgap Reference ◽  
28 Nm

scholarly journals -81dB PSRR regulated cascode fully MOS bandgap reference for power management in RF energy harvesting systems

2019 ◽  
Vol 14 (2) ◽  
pp. 706
Author(s):  
M. K.Zulkalnain ◽  
N. A.Kamsani ◽  
R. M.Sidek ◽  
F. Z.Rokhani ◽  
S. J.Hashim ◽  
...  
Keyword(s):  
Power Management ◽  
Clean Energy ◽  
Cmos Technology ◽  
Low Noise ◽  
Noise Power ◽  
Threshold Region ◽  
Bandgap Reference ◽  
Main Challenge ◽  
Harvesting Systems ◽  
Iot Devices

In the midst of technological advance where everything is connected via the internet, IoT is emerging as a potential solution to everything, ranging from health wearables to smart city. An RFEH power management system has promising benefits that could further improve the powering of IoT devices as it has potential for clean energy as well as other advantages which consists of a rectifier, bandgap reference and LDO as the main core. However, the main challenge is supplying clean and low noise power to sensitive circuits such as low power sensors, VCOs and PLLs. A high PSRR bandgap reference that rejects noise at the power supply is needed so that the circuitry powered by RFEH systems would be able to function properly. This paper presents a bandgap with MOS PTAT and CTAT extraction achieving a PSRR of -81dB at a V<sub>ref</sub> of 0.415V was designed on 130nm CMOS technology targeting IoT RFEH devices that operate at sub-threshold and near-threshold region that exhibits improvement over the base design.

scholarly journals An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology

Electronics ◽  
2021 ◽  
Vol 10 (14) ◽  
pp. 1686
Author(s):  
Jian Chen ◽  
Wei Zhang ◽  
Qingqing Sun ◽  
Lizheng Liu
Keyword(s):  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Noise Power ◽  
Voltage Controlled Oscillator ◽  
Serial Link ◽  
Ldo Regulator ◽  
28 Nm

This study presents an inductance capacitance (LC) phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) and a noise-reduced low-dropout (LDO) regulator, which was used in four-lane multiprotocol serial link applications. The dual VCO architecture can increase the total frequency-tuning range to ensure that the LC PLL achieves multiprotocol serial link coverage from 8 to 12.5 Gbps. Two switch capacitor array-based LC VCOs have a large frequency-tuning range and small VCO gain. The noise-reduced LDO regulator provides a very low-noise power supply to the VCO. The active area occupied by the proposed LC PLL in UMC 28-nm 1P10M complementary metal–oxide–semiconductor (CMOS) technology is 0.25 mm2. The phase noise of the VCO at 1 MHz is −108.1 dBc/Hz. The power consumption of the LC PLL with a 1.8-V supply is 16.5 mW.

A Low-Noise W-Band Receiver in a 28-nm CMOS Technology

2021 ◽  
pp. 1-4
Author(s):  
Daniel Reiter ◽  
Hao Li ◽  
Badou Sene ◽  
Nils Pohl
Keyword(s):  
Cmos Technology ◽  
Low Noise ◽  
W Band ◽  
28 Nm

60 GHz-Band Low-Noise Amplifier

2017 ◽  
Vol 26 (05) ◽  
pp. 1750075 ◽  
Author(s):  
Najam Muhammad Amin ◽  
Lianfeng Shen ◽  
Zhi-Gong Wang ◽  
Muhammad Ovais Akhter ◽  
Muhammad Tariq Afridi
Keyword(s):  
Transmission Line ◽  
Quality Factor ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Constant Current ◽  
60 Ghz ◽  
Frequency Range ◽  
Constant Current Density ◽  
Chip Area

This paper presents the design of a 60[Formula: see text]GHz-band LNA intended for the 63.72–65.88[Formula: see text]GHz frequency range (channel-4 of the 60[Formula: see text]GHz band). The LNA is designed in a 65-nm CMOS technology and the design methodology is based on a constant-current-density biasing scheme. Prior to designing the LNA, a detailed investigation into the transistor and passives performances at millimeter-wave (MMW) frequencies is carried out. It is shown that biasing the transistors for an optimum noise figure performance does not degrade their power gain significantly. Furthermore, three potential inductive transmission line candidates, based on coplanar waveguide (CPW) and microstrip line (MSL) structures, have been considered to realize the MMW interconnects. Electromagnetic (EM) simulations have been performed to design and compare the performances of these inductive lines. It is shown that the inductive quality factor of a CPW-based inductive transmission line ([Formula: see text] is more than 3.4 times higher than its MSL counterpart @ 65[Formula: see text]GHz. A CPW structure, with an optimized ground-equalizing metal strip density to achieve the highest inductive quality factor, is therefore a preferred choice for the design of MMW interconnects, compared to an MSL. The LNA achieves a measured forward gain of [Formula: see text][Formula: see text]dB with good input and output impedance matching of better than [Formula: see text][Formula: see text]dB in the desired frequency range. Covering a chip area of 1256[Formula: see text][Formula: see text]m[Formula: see text]m including the pads, the LNA dissipates a power of only 16.2[Formula: see text]mW.

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

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