High gain V-band active-integrated antenna transmitter using Darlington pair VCO in 0.13 [micro sign]m CMOS process

2010 ◽  
Vol 46 (5) ◽  
pp. 321 ◽  
Author(s):  
H.-K. Chiou ◽  
I-S. Chen ◽  
W.-C. Chen
Keyword(s):  
High Gain ◽  
Cmos Process ◽  
V Band ◽  
Active Integrated Antenna ◽  
Integrated Antenna

FDTD simulation of active integrated antenna

1997 ◽  
Vol 33 (25) ◽  
pp. 2091 ◽  
Author(s):  
C. Kalialakis ◽  
M.J. Cryan ◽  
P.S. Hall ◽  
P. Gardner
Keyword(s):  
Fdtd Simulation ◽  
Active Integrated Antenna ◽  
Integrated Antenna

scholarly journals A Sigma-Delta ADC for Signal Conditioning IC of Automotive Piezo-Resistive Pressure Sensors with over 80 dB SNR

Sensors ◽  
2018 ◽  
Vol 18 (12) ◽  
pp. 4199 ◽  
Author(s):  
Behnam Samadpoor Rikan ◽  
Sang-Yun Kim ◽  
Nabeel Ahmad ◽  
Hamed Abbasizadeh ◽  
Muhammad Riaz Ur Rehman ◽  
...  
Keyword(s):  
Input Signal ◽  
Flicker Noise ◽  
Signal To Noise Ratio ◽  
Pressure Sensors ◽  
High Gain ◽  
Cmos Process ◽  
Signal Conditioning ◽  
Sigma Delta ◽  
Cic Filter ◽  
Decimation Filter

This paper presents a second-order discrete-time Sigma-Delta (SD) Analog-to-Digital Converter (ADC) with over 80 dB Signal to Noise Ratio (SNR), which is applied in a signal conditioning IC for automotive piezo-resistive pressure sensors. To reduce the flicker noise of the structure, choppers are used in every stage of the high gain amplifiers. Besides, to reduce the required area and power, only the CIC filter structure is adopted as a decimation filter. This filter has a configurable structure that can be applied to different data rates and input signal bandwidths. The proposed ADC was fabricated and measured in a 0.18-µm CMOS process. Due to the application of only a CIC filter, the total active area of the SD-ADC and reference generator is 0.49 mm2 where the area of the decimation filter is only 0.075 mm2. For the input signal bandwidth of 1.22 kHz, it achieved over 80 dB SNR in a 2.5 MHz sampling frequency while consuming 646 µW power.

$V$ -band $\times 8$ Frequency Multiplier With Optimized Structure and High Spectral Purity Using 65-nm CMOS Process

2017 ◽  
Vol 27 (5) ◽  
pp. 506-508 ◽  
Author(s):  
Jae-Sun Kim ◽  
Hyun-Myung Oh ◽  
Chul Woo Byeon ◽  
Ju Ho Son ◽  
Jeong Ho Lee ◽  
...  
Keyword(s):  
Frequency Multiplier ◽  
Cmos Process ◽  
Spectral Purity ◽  
V Band
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