Ultra fast locking, low jitter, auto-ranging phase-locked loop

Author(s):  
E. O'Sullivan ◽  
I. Kennedy ◽  
D. McSweeney ◽  
B. O'Regan ◽  
P.K. Chandrasekar ◽  
...  
Keyword(s):  
2017 ◽  
Vol 63 (3) ◽  
pp. 336-345
Author(s):  
Jin Wu ◽  
Chao Wang ◽  
Shu-fang Shi ◽  
Xiang-rong Yu ◽  
Li-xia Zheng ◽  
...  

2018 ◽  
Vol 7 (2.12) ◽  
pp. 348
Author(s):  
Rajeshwari D S ◽  
P V Rao ◽  
Ramesh Karmungi

This paper presents design and simulation of charge pump architectures for 10GHz Charge Pump Phase locked Loop. Differential delay cell VCO with symmetric load and Programmable frequency divider are efficiently implemented in loop. Able to achieve Peak jitter of the Divider 10ns, Peak jitter of VCO 205ps at 1GHz.Charge pump is analysed in loop by reduced current mismatch using improved high swing cascode structure including start up circuitand it has low turn ON voltage and high ouput impedance to provide stable voltage.Charge pump results current mismatch less than 0.05%.10GHz DPLL is simulated with 65nm techonology, 1.2V and tsmc foundary model files


2006 NORCHIP ◽  
2006 ◽  
Author(s):  
Eugene O'Sullivan ◽  
Carel J Lombaard ◽  
Dermot McSweeney ◽  
Brendan O'Regan ◽  
Ian Kennedy ◽  
...  
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2011 ◽  
Vol 32 (3) ◽  
pp. 035004 ◽  
Author(s):  
Niansong Mei ◽  
Yu Sun ◽  
Bo Lu ◽  
Yaohua Pan ◽  
Yumei Huang ◽  
...  

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