A novel method of twiddle factor generation of the FFT processor for OFDM system

Author(s):  
Qing Liu ◽  
Yanping Yu ◽  
Kuang Wang
2014 ◽  
Vol 573 ◽  
pp. 176-180
Author(s):  
G. Kavitha ◽  
B. Kirthiga ◽  
N. Kirubanandasarathy

In this paper, an area-efficient low power fast fourier transform (FFT) processor is proposed for multi input multi output-orthogonal frequency division multiplexing (MIMO-OFDM) in wireless communication system. It consists of a modified architecture of radix-2 algorithm which is described as modified radix-2 multipath delay commutation (MOD-R2MDC). The OFDM receiver with modified R2MDC (MOD-R2MDC) FFT was designed by Hardware Description Language (HDL) coding The Xilinx ISE Design Suite 10.1 is used as a synthesis tool for getting the power and area. The Model-Sim 6.3c is used for simulation. Also the existing OFDM system has been tested with these FFT algorithms and their performances were analyzed with respect to occupancy area in FPGA and power consumption. A low-power and area efficient architecture enables the real-time operations of MIMO OFDM system.


2013 ◽  
Vol 49 (23) ◽  
pp. 1443-1445 ◽  
Author(s):  
Hyeong‐Ju Kang ◽  
Jong‐Yeol Lee ◽  
Ji‐Hoon Kim

2011 ◽  
Vol 12 (12) ◽  
pp. 1021-1030 ◽  
Author(s):  
Ji-nan Leng ◽  
Lei Xie ◽  
Hui-fang Chen ◽  
Kuang Wang

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