Design of a 1.8 V, 10-bit 130+MS/s time-interleaved non-scaled pipeline ADC in 0.18 μm CMOS

2005 ◽  
Author(s):  
B. Vaz
Keyword(s):  
Pipeline Adc ◽  
Time Interleaved

A 12 bit 1.6 GS/s BiCMOS 2×2 hierarchical time-interleaved pipeline ADC

2013 ◽  
Author(s):  
Manar El-Chammas ◽  
Xiaopeng Li ◽  
Shigenobu Kimura ◽  
Kenneth Maclean ◽  
Jake Hu ◽  
...  
Keyword(s):  
Pipeline Adc ◽  
Time Interleaved

scholarly journals An Optimization-Based Reconfigurable Design for a 6-Bit 11-MHz Parallel Pipeline ADC with Double-Sampling S&H

2012 ◽  
Vol 2012 ◽  
pp. 1-17 ◽  
Author(s):  
Wilmar Carvajal ◽  
Wilhelmus Van Noije
Keyword(s):  
Analog Circuits ◽  
Bottom Plate ◽  
Pipeline Adc ◽  
Digital Correction ◽  
Fully Differential ◽  
Reconfigurable Design ◽  
Parallel Pipeline ◽  
Block Level ◽  
Differential Circuits ◽  
Time Interleaved

This paper presents a 6 bit, 11 MS/s time-interleaved pipeline A/D converter design. The specification process, from block level to elementary circuits, is gradually covered to draw a design methodology. Both power consumption and mismatch between the parallel chain elements are intended to be reduced by using some techniques such as double and bottom-plate sampling, fully differential circuits, RSD digital correction, and geometric programming (GP) optimization of the elementary analog circuits (OTAs and comparators) design. Prelayout simulations of the complete ADC are presented to characterize the designed converter, which consumes 12 mW while sampling a 500 kHz input signal. Moreover, the block inside the ADC with the most stringent requirements in power, speed, and precision was sent to fabrication in a CMOS 0.35 μm AMS technology, and some postlayout results are shown.

A Time-Interleaved SAR Assisted Pipeline ADC With a Bias-Enhanced Ring Amplifier

2018 ◽  
Vol 65 (11) ◽  
pp. 1584-1588 ◽  
Author(s):  
Yongzhen Chen ◽  
Jingjing Wang ◽  
Hang Hu ◽  
Fan Ye ◽  
Junyan Ren
Keyword(s):  
Pipeline Adc ◽  
Time Interleaved

A 12b 100 MS/s Three-Step Hybrid Pipeline ADC Based on Time-Interleaved SAR ADCs

2014 ◽  
Vol 14 (2) ◽  
pp. 189-197 ◽  
Author(s):  
Jun-Sang Park ◽  
Tai-Ji An ◽  
Suk-Hee Cho ◽  
Yong-Min Kim ◽  
Gil-Cho Ahn ◽  
...  
Keyword(s):  
Pipeline Adc ◽  
Time Interleaved

A 12 Bit 1.6 GS/s BiCMOS 2×2 Hierarchical Time-Interleaved Pipeline ADC

2014 ◽  
Vol 49 (9) ◽  
pp. 1876-1885 ◽  
Author(s):  
Manar El-Chammas ◽  
Xiaopeng Li ◽  
Shigenobu Kimura ◽  
Kenneth Maclean ◽  
Jake Hu ◽  
...  
Keyword(s):  
Pipeline Adc ◽  
Time Interleaved
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