Lowering the Error Floor of LDPC Codes Based on Bit-Rectification Strategy

IET 8th International Conference on Wireless, Mobile & Multimedia Networks ◽

10.1049/cp.2019.1150 ◽

2019 ◽

Author(s):

Hui Xue ◽

Lijun Zhang

Keyword(s):

Ldpc Codes ◽

Error Floor

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A Deep Learning-Aided Post-Processing Scheme to Lower the Error Floor of LDPC Codes

2020 IEEE 20th International Conference on Communication Technology (ICCT) ◽

10.1109/icct50939.2020.9295784 ◽

2020 ◽

Author(s):

Jiajun He

Keyword(s):

Deep Learning ◽

Ldpc Codes ◽

Error Floor ◽

Post Processing ◽

Processing Scheme

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Algebraic Quasi-Cyclic LDPC Codes: Construction, Low Error-Floor, Large Girth and a Reduced-Complexity Decoding Scheme

IEEE Transactions on Communications ◽

10.1109/tcomm.2014.2339329 ◽

2014 ◽

Vol 62 (8) ◽

pp. 2626-2637 ◽

Cited By ~ 67

Author(s):

Juane Li ◽

Keke Liu ◽

Shu Lin ◽

Khaled Abdel-Ghaffar

Keyword(s):

Ldpc Codes ◽

Error Floor ◽

Large Girth ◽

Reduced Complexity

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Lowering the Error Floor of LDPC Codes by a Two-stage Hybrid Decoding Algorithm

2007 Second International Conference on Communications and Networking in China ◽

10.1109/chinacom.2007.4469460 ◽

2007 ◽

Author(s):

Yueguang Bian ◽

Youzheng Wang ◽

Jing Wang

Keyword(s):

Ldpc Codes ◽

Error Floor ◽

Decoding Algorithm ◽

Two Stage

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Structured LDPC codes for high-density recording: large girth and low error floor

IEEE Transactions on Magnetics ◽

10.1109/tmag.2005.861748 ◽

2006 ◽

Vol 42 (2) ◽

pp. 208-213 ◽

Cited By ~ 41

Author(s):

J. Lu ◽

J.M.F. Moura

Keyword(s):

Ldpc Codes ◽

High Density ◽

Error Floor ◽

High Density Recording ◽

Large Girth

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New PEG algorithm with low error floor for construction of irregular LDPC codes

2015 IEEE International Conference on Computer and Communications (ICCC) ◽

10.1109/compcomm.2015.7387584 ◽

2015 ◽

Cited By ~ 1

Author(s):

Feijin Shi ◽

Shuangshuang Han

Keyword(s):

Ldpc Codes ◽

Error Floor ◽

Irregular Ldpc Codes

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Quantized min-sum decoders with low error floor for LDPC codes

2012 IEEE International Symposium on Information Theory Proceedings ◽

10.1109/isit.2012.6284049 ◽

2012 ◽

Cited By ~ 23

Author(s):

Xiaojie Zhang ◽

Paul H. Siegel

Keyword(s):

Ldpc Codes ◽

Error Floor

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Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2014.2304660 ◽

2014 ◽

Vol 61 (7) ◽

pp. 2150-2158 ◽

Cited By ~ 28

Author(s):

Fabian Angarita ◽

Javier Valls ◽

Vicenc Almenar ◽

Vicente Torres

Keyword(s):

Ldpc Codes ◽

Error Floor ◽

Reduced Complexity

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Fast and Accurate Error Floor Estimation of Quantized Iterative Decoders for Variable-Regular LDPC Codes

IEEE Communications Letters ◽

10.1109/lcomm.2014.2331070 ◽

2014 ◽

Vol 18 (8) ◽

pp. 1283-1286 ◽

Cited By ~ 6

Author(s):

Sina Tolouei ◽

Amir H. Banihashemi

Keyword(s):

Ldpc Codes ◽

Error Floor ◽

Iterative Decoders

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A survey of error floor of LDPC codes

2011 6th International ICST Conference on Communications and Networking in China (CHINACOM) ◽

10.1109/chinacom.2011.6158120 ◽

2011 ◽

Author(s):

Yejun He ◽

Jie Yang ◽

Jiawei Song

Keyword(s):

Ldpc Codes ◽

Error Floor

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Field programmable gate array-based investigation of the error floor of low density parity check (LDPC) codes for magnetic recording channel

INTERMAG Asia 2005. Digests of the IEEE International Magnetics Conference, 2005. ◽

10.1109/intmag.2005.1464236 ◽

2005 ◽

Author(s):

Lingyan Sun ◽

Hongwei Song ◽

B.V.K. Vijaya Kumar ◽

Z. Keirn

Keyword(s):

Magnetic Recording ◽

Field Programmable Gate Array ◽

Ldpc Codes ◽

Low Density ◽

Parity Check ◽

Error Floor ◽

Low Density Parity Check ◽

Field Programmable ◽

Recording Channel ◽

Gate Array

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