A TADF compound with high-contrast mechano-responsive fluorescence on/off switching for both sequential and combinational logic gates

2019 ◽  
Vol 7 (12) ◽  
pp. 3522-3528 ◽  
Author(s):  
Sunil Kumar Baburao Mane ◽  
Yingxiao Mu ◽  
Zhiyong Yang ◽  
Eethamukkala Ubba ◽  
Naghma Shaishta ◽  
...  
Keyword(s):  
Logic Gates ◽  
Combinational Logic ◽  
High Contrast

Both sequential and combinational type logic gates can be achieved within a TADF luminogen with high-contrast mechano-responsive luminescence.

A probabilistic model for stuck-on faults in combinational logic gates

2016 ◽  
Author(s):  
Rafael B. Schivittz ◽  
Denis T. Franco ◽  
Cristina Meinhardt ◽  
Paulo F. Butzen
Keyword(s):  
Probabilistic Model ◽  
Logic Gates ◽  
Combinational Logic

Combinational Logic Gates

2020 ◽  
pp. 97-132
Author(s):  
Dale Patrick ◽  
Stephen Fardo ◽  
Vigyan ‘Vigs’ Chandra
Keyword(s):  
Logic Gates ◽  
Combinational Logic

scholarly journals Biased Mutation and Tournament Selection Approaches for Designing Combinational Logic Circuits via Cartesian Genetic Programming

2018 ◽  
Author(s):  
José Eduardo H. Da Silva ◽  
Francisco A. L. Manfrini ◽  
Heder S. Bernardino ◽  
Helio J. C. Barbosa
Keyword(s):  
Genetic Programming ◽  
Objective Function ◽  
Logic Gates ◽  
Logic Circuits ◽  
Combinational Logic ◽  
Cartesian Genetic Programming ◽  
Mutation Strategy ◽  
Tournament Selection ◽  
Combinational Logic Circuits ◽  
Better Than

Cartesian Genetic Programming (CGP) is often applied to design combinational logic circuits. However, there is no consensus in the literature regarding the more appropriate objective function when it is desired to minimize the number of logic gates of the circuit. Thus, we analyze here two strategies: the minimization of the number of logic gates and the maximization of the number of wire gates. Additionally, a biased mutation strategy for CGP, which were previously presented and tested only to find a feasible solution, are extended in this paper for the subsequent optimization step. Several configurations were proposed and tested varying objective function and selection schemes. Compu- tational experiments are conducted with some benchmark circuits to relatively compare the proposed methods, and the results obtained are better than those found by the other techniques considered here.

Ternary Electronic Logic Systems Automation: A Novel Study Based on VHDL Language – Second Part: Ternary Combination Logic Components

2018 ◽  
Vol 23 (2) ◽  
pp. 1-30
Author(s):  
عبدالله علي قاسم الحميدي ◽  
عبدالرقيب عبده أسعد
Keyword(s):  
Logic Gates ◽  
Combinational Logic ◽  
Software Library ◽  
Ternary Logic ◽  
Xor Gate ◽  
Logic Systems ◽  
Electronic Logic

In this paper, the second part of the software library for the Ternary combinational logic components will be built based on VHDL language starting by the TXOR (Ternary XOR gate) and ending by the TPA (Ternary Parallel Adder). This second part is an extension to the library given in the first part of the study which was about the basic Ternary Logic Gates [1]. Keywords: Ternary logic, Ternary combinational logic components, VHDL language.

A Novel Evolutionary Method for Designing Optimized Multifunctional Logic Modules

2013 ◽  
Vol 2 (2) ◽  
pp. 55
Author(s):  
Mehdi Anjomshoa ◽  
Ali Mahani
Keyword(s):  
Heuristic Method ◽  
Logic Gates ◽  
Imperialist Competitive Algorithm ◽  
Arithmetic Functions ◽  
Combinational Logic ◽  
Specific Function ◽  
Circuit Structure ◽  
Simulation Results ◽  
Logic Modules ◽  
Ica Algorithm

In this paper, we proposed a novel heuristic method based on Imperialist competitive Algorithm (ICA) to design combinational logic modules which performing different arithmetic functions. According to conventional methods, for multi functional circuit, a distinct circuit is designed for each specific function and then all of them are combined together with multiplexer(s) to have desired circuit. But in our proposed method the whole circuit structure is designed and optimized in one procedure by ICA Algorithm. We tried to optimize the area of circuit by reducing the number of transistors forming logic gates. Simulation results show that our method significantly reduces the number of transistors and gates and accordingly the circuit area.

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